{"id":"https://openalex.org/W2023400509","doi":"https://doi.org/10.1109/tvlsi.2010.2092795","title":"Analyzing Potential Throughput Improvement of Power- and Thermal-Constrained Multicore Processors by Exploiting DVFS and PCPG","display_name":"Analyzing Potential Throughput Improvement of Power- and Thermal-Constrained Multicore Processors by Exploiting DVFS and PCPG","publication_year":2011,"publication_date":"2011-02-03","ids":{"openalex":"https://openalex.org/W2023400509","doi":"https://doi.org/10.1109/tvlsi.2010.2092795","mag":"2023400509"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2010.2092795","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2010.2092795","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035555716","display_name":"Jungseob Lee","orcid":"https://orcid.org/0000-0002-9431-6342"},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jungseob Lee","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI, USA","Dept. of Electr. & Comput. Eng., Univ. of Wisconsin, Madison, WI, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI, USA","institution_ids":["https://openalex.org/I135310074"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Wisconsin, Madison, WI, USA#TAB#","institution_ids":["https://openalex.org/I135310074"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037648751","display_name":"Nam Sung Kim","orcid":"https://orcid.org/0000-0002-0442-5634"},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nam Sung Kim","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI, USA","Dept. of Electr. & Comput. Eng., Univ. of Wisconsin, Madison, WI, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI, USA","institution_ids":["https://openalex.org/I135310074"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Wisconsin, Madison, WI, USA#TAB#","institution_ids":["https://openalex.org/I135310074"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5035555716"],"corresponding_institution_ids":["https://openalex.org/I135310074"],"apc_list":null,"apc_paid":null,"fwci":1.0075,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.77197671,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"20","issue":"2","first_page":"225","last_page":"235"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/frequency-scaling","display_name":"Frequency scaling","score":0.8731371164321899},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.8319294452667236},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6681274771690369},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5912750363349915},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.5743612051010132},{"id":"https://openalex.org/keywords/single-core","display_name":"Single-core","score":0.526427149772644},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.44338810443878174},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.43786856532096863},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.39839091897010803},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3334035873413086},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.18774113059043884},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13890811800956726},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.102719247341156}],"concepts":[{"id":"https://openalex.org/C157742956","wikidata":"https://www.wikidata.org/wiki/Q3237776","display_name":"Frequency scaling","level":3,"score":0.8731371164321899},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.8319294452667236},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6681274771690369},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5912750363349915},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.5743612051010132},{"id":"https://openalex.org/C2780365336","wikidata":"https://www.wikidata.org/wiki/Q25047934","display_name":"Single-core","level":2,"score":0.526427149772644},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.44338810443878174},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.43786856532096863},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.39839091897010803},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3334035873413086},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.18774113059043884},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13890811800956726},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.102719247341156},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2010.2092795","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2010.2092795","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8500000238418579,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W1969008267","https://openalex.org/W1995516682","https://openalex.org/W2000335122","https://openalex.org/W2033443176","https://openalex.org/W2043340768","https://openalex.org/W2059807497","https://openalex.org/W2059941121","https://openalex.org/W2069345435","https://openalex.org/W2078423579","https://openalex.org/W2079942837","https://openalex.org/W2086202544","https://openalex.org/W2096805904","https://openalex.org/W2097273347","https://openalex.org/W2099714261","https://openalex.org/W2101554015","https://openalex.org/W2112085716","https://openalex.org/W2126394324","https://openalex.org/W2132100607","https://openalex.org/W2140761742","https://openalex.org/W2146159705","https://openalex.org/W2150283124","https://openalex.org/W2150526221","https://openalex.org/W2154169726","https://openalex.org/W2167840018","https://openalex.org/W2170509664","https://openalex.org/W2171825402","https://openalex.org/W3150134984","https://openalex.org/W3152109627","https://openalex.org/W4242466841","https://openalex.org/W4250692521","https://openalex.org/W4255868121","https://openalex.org/W6677314723"],"related_works":["https://openalex.org/W2332054630","https://openalex.org/W2590100594","https://openalex.org/W2475077126","https://openalex.org/W2151223307","https://openalex.org/W2142016460","https://openalex.org/W2154351074","https://openalex.org/W2898122376","https://openalex.org/W1987176048","https://openalex.org/W2023400509","https://openalex.org/W2154169726"],"abstract_inverted_index":{"Process":[0],"variability":[1],"from":[2],"a":[3,26,52,79,159,183,238],"range":[4],"of":[5,18,43,59,89,171,182,207,237],"sources":[6],"is":[7,11],"growing":[8],"as":[9],"technology":[10,163],"scaled":[12],"below":[13],"65":[14],"nm,":[15],"increasing":[16],"variations":[17,211,221,232],"transistor":[19],"delay":[20],"and":[21,28,39,91,99,136,139,152,174,201,218],"leakage":[22,219],"current":[23],"both":[24],"within":[25,149],"die":[27,54],"across":[29],"dies.":[30],"This,":[31],"in":[32,51,78,82,128,222],"turn,":[33],"negatively":[34],"impacts":[35],"maximum":[36,175],"operating":[37,176],"frequency":[38,177,217,231],"total":[40],"power":[41,97,122,135,220],"consumption":[42],"processors.":[44,131,224],"Meanwhile,":[45],"manufacturers":[46],"have":[47,70,107],"integrated":[48],"more":[49],"cores":[50,77,119,142,173],"single":[53],"to":[55,74,110,143,193,203,214,243],"improve":[56,179,234],"the":[57,87,169,180,205,235],"throughput":[58,88,181,199,236],"processors":[60,94],"running":[61,186],"highly-parallel":[62],"workloads.":[63],"However,":[64],"many":[65],"existing":[66],"workloads":[67,187],"do":[68,105],"not":[69,106],"high":[71],"enough":[72,108],"parallelism":[73,109,190],"exploit":[75],"multiple":[76],"processor.":[80],"First,":[81],"this":[83],"paper,":[84],"we":[85,104,115,196],"maximize":[86],"power-":[90],"thermal-constrained":[92],"multicore":[93,130,223],"using":[95,120,158],"per-core":[96,121],"gating":[98],"dynamic":[100],"voltage/frequency":[101,147],"scaling.":[102],"When":[103],"effectively":[111],"use":[112],"all":[113],"cores,":[114],"turn":[116],"off":[117],"some":[118],"gates":[123],"that":[124,166,212,228],"are":[125],"already":[126],"available":[127],"commercial":[129],"This":[132],"provides":[133],"extra":[134],"thermal":[137],"headroom,":[138],"allows":[140],"active":[141,172],"run":[144],"faster":[145],"through":[146],"scaling":[148,154],"power,":[150],"thermal,":[151],"voltage":[153],"limits.":[155],"Our":[156,225],"analysis":[157,200,226],"32":[160],"nm":[161],"predictive":[162],"model":[164],"demonstrates":[165],"jointly":[167],"optimizing":[168],"number":[170],"can":[178,233],"16-core":[184,239],"processor":[185,240],"with":[188],"limited":[189],"by":[191,241],"up":[192,242],"14%.":[194],"Second,":[195],"extend":[197],"our":[198],"optimization":[202],"consider":[204],"impact":[206],"within-die":[208],"spatial":[209],"process":[210],"lead":[213],"considerable":[215],"core-to-core":[216,230],"shows":[227],"exploiting":[229],"57%.":[244]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
