{"id":"https://openalex.org/W2102986659","doi":"https://doi.org/10.1109/tvlsi.2010.2091974","title":"Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits","display_name":"Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits","publication_year":2010,"publication_date":"2010-12-22","ids":{"openalex":"https://openalex.org/W2102986659","doi":"https://doi.org/10.1109/tvlsi.2010.2091974","mag":"2102986659"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2010.2091974","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2010.2091974","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://research.tue.nl/en/publications/ea31d54f-2836-4df1-be01-ac68a3f84a68","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061465128","display_name":"Maurice Meijer","orcid":null},"institutions":[{"id":"https://openalex.org/I109147379","display_name":"NXP (Netherlands)","ror":"https://ror.org/059be4e97","country_code":"NL","type":"company","lineage":["https://openalex.org/I109147379"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"Maurice Meijer","raw_affiliation_strings":["Central Research and Development Division, NXP Semiconductors, Eindhoven, Netherlands","Central R&D Div., NXP Semicond., Eindhoven, Netherlands"],"affiliations":[{"raw_affiliation_string":"Central Research and Development Division, NXP Semiconductors, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I109147379"]},{"raw_affiliation_string":"Central R&D Div., NXP Semicond., Eindhoven, Netherlands","institution_ids":["https://openalex.org/I109147379"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050945839","display_name":"Jos\u00e9 Pineda de Gyvez","orcid":"https://orcid.org/0000-0002-0723-7065"},"institutions":[{"id":"https://openalex.org/I109147379","display_name":"NXP (Netherlands)","ror":"https://ror.org/059be4e97","country_code":"NL","type":"company","lineage":["https://openalex.org/I109147379"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Jos\u00e9 Pineda de Gyvez","raw_affiliation_strings":["Central Research and Development Division, NXP Semiconductors, Eindhoven, Netherlands"],"affiliations":[{"raw_affiliation_string":"Central Research and Development Division, NXP Semiconductors, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I109147379"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5061465128"],"corresponding_institution_ids":["https://openalex.org/I109147379"],"apc_list":null,"apc_paid":null,"fwci":0.2886,"has_fulltext":false,"cited_by_count":29,"citation_normalized_percentile":{"value":0.64761099,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"20","issue":"1","first_page":"42","last_page":"51"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dimensioning","display_name":"Dimensioning","score":0.7003207206726074},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6634966731071472},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5866278409957886},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5489453077316284},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.5176070928573608},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.47380584478378296},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.46731632947921753},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.45501744747161865},{"id":"https://openalex.org/keywords/oversampling","display_name":"Oversampling","score":0.4399188756942749},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4197431802749634},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.41680198907852173},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.38916900753974915},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.38772451877593994},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.30394989252090454},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24531537294387817},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21183863282203674},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18351173400878906},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.10176172852516174}],"concepts":[{"id":"https://openalex.org/C89714869","wikidata":"https://www.wikidata.org/wiki/Q2280470","display_name":"Dimensioning","level":2,"score":0.7003207206726074},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6634966731071472},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5866278409957886},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5489453077316284},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.5176070928573608},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.47380584478378296},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.46731632947921753},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.45501744747161865},{"id":"https://openalex.org/C197323446","wikidata":"https://www.wikidata.org/wiki/Q331222","display_name":"Oversampling","level":3,"score":0.4399188756942749},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4197431802749634},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.41680198907852173},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.38916900753974915},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.38772451877593994},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.30394989252090454},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24531537294387817},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21183863282203674},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18351173400878906},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.10176172852516174},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C146978453","wikidata":"https://www.wikidata.org/wiki/Q3798668","display_name":"Aerospace engineering","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tvlsi.2010.2091974","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2010.2091974","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:pure.tue.nl:openaire/ea31d54f-2836-4df1-be01-ac68a3f84a68","is_oa":true,"landing_page_url":"https://research.tue.nl/en/publications/ea31d54f-2836-4df1-be01-ac68a3f84a68","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Meijer, M & Pineda de Gyvez, J 2012, 'Body-bias-driven design strategy for area and performance efficient CMOS circuits', IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 1, pp. 42-51. https://doi.org/10.1109/TVLSI.2010.2091974","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:tue:oai:pure.tue.nl:publications/ea31d54f-2836-4df1-be01-ac68a3f84a68","is_oa":true,"landing_page_url":"https://research.tue.nl/nl/publications/ea31d54f-2836-4df1-be01-ac68a3f84a68","pdf_url":null,"source":{"id":"https://openalex.org/S4306401843","display_name":"Data Archiving and Networked Services (DANS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1322597698","host_organization_name":"Royal Netherlands Academy of Arts and Sciences","host_organization_lineage":["https://openalex.org/I1322597698"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(1), 42 - 51. Institute of Electrical and Electronics Engineers","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:pure.tue.nl:openaire/ea31d54f-2836-4df1-be01-ac68a3f84a68","is_oa":true,"landing_page_url":"https://research.tue.nl/en/publications/ea31d54f-2836-4df1-be01-ac68a3f84a68","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Meijer, M & Pineda de Gyvez, J 2012, 'Body-bias-driven design strategy for area and performance efficient CMOS circuits', IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 1, pp. 42-51. https://doi.org/10.1109/TVLSI.2010.2091974","raw_type":"info:eu-repo/semantics/publishedVersion"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1554898868","https://openalex.org/W2019487421","https://openalex.org/W2035925997","https://openalex.org/W2040228876","https://openalex.org/W2046737467","https://openalex.org/W2088115909","https://openalex.org/W2097466426","https://openalex.org/W2098736822","https://openalex.org/W2101848657","https://openalex.org/W2105035472","https://openalex.org/W2105545647","https://openalex.org/W2105597240","https://openalex.org/W2115435370","https://openalex.org/W2118404416","https://openalex.org/W2120527248","https://openalex.org/W2146743175","https://openalex.org/W2150526221","https://openalex.org/W2150713987","https://openalex.org/W2162714421","https://openalex.org/W2172629440","https://openalex.org/W2788930157","https://openalex.org/W4240067961","https://openalex.org/W4242819225","https://openalex.org/W4245614799","https://openalex.org/W6677855490","https://openalex.org/W6681979597","https://openalex.org/W6683731785"],"related_works":["https://openalex.org/W2119670668","https://openalex.org/W1987400600","https://openalex.org/W2767258391","https://openalex.org/W1986902523","https://openalex.org/W2161666177","https://openalex.org/W1981302138","https://openalex.org/W2070693700","https://openalex.org/W1967188269","https://openalex.org/W962052505","https://openalex.org/W4206210640"],"abstract_inverted_index":{"Worst-case":[0],"design":[1,29,65,142],"uses":[2],"extreme":[3],"process":[4],"corner":[5],"conditions":[6],"which":[7],"rarely":[8],"occur.":[9],"This":[10],"limits":[11],"maximum":[12],"speed":[13],"specifications":[14],"and":[15,118,124,168,174],"costs":[16],"additional":[17],"power":[18,126,176],"due":[19],"to":[20,115,122,130,165,172,180],"area":[21,117,167],"over-dimensioning":[22,54],"during":[23],"synthesis.":[24],"We":[25,88],"present":[26],"a":[27,47,136],"new":[28,91],"synthesis":[30],"strategy":[31],"for":[32,148],"digital":[33],"CMOS":[34],"circuits":[35],"that":[36,75],"makes":[37],"use":[38],"of":[39,62,79,85,128,178],"forward":[40],"body":[41],"biasing.":[42],"Our":[43],"approach":[44],"renders":[45],"consistently":[46],"better":[48],"performance-per-area":[49,112,162],"ratio":[50],"by":[51,72],"constraining":[52],"circuit":[53,57],"without":[55,132,182],"sacrificing":[56],"performance.":[58],"An":[59],"in-depth":[60],"analysis":[61],"the":[63,80,86],"body-bias-driven":[64,141],"theory":[66],"is":[67,70],"provided.":[68],"It":[69],"complemented":[71],"an":[73],"algorithm":[74],"enables":[76],"fast":[77],"reconstruction":[78],"area-clock":[81],"period":[82],"tradeoff":[83],"curve":[84],"design.":[87],"validated":[89],"these":[90],"concepts":[92],"through":[93],"industrial":[94],"processor":[95],"designs":[96],"in":[97],"90-nm":[98],"low-power":[99],"CMOS.":[100],"For":[101],"standard-":[102],"<i":[103,150],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[104,107,151,154],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">V</i>":[105,152],"<sub":[106,153],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">th</sub>":[108,155],"implementations,":[109],"we":[110,160],"observed":[111,161],"improvements":[113,163],"up":[114,121,129,164,171,179],"40%,":[116,173],"leakage":[119,169],"reductions":[120,170],"30%,":[123],"dynamic":[125,175],"savings":[127,177],"10%":[131],"performance":[133,183],"penalties":[134],"as":[135],"benefit":[137],"from":[138],"our":[139],"proposed":[140],"strategy.":[143],"The":[144],"benefits":[145],"are":[146],"larger":[147],"high-":[149],"implementations.":[156],"In":[157],"this":[158],"case,":[159],"90%,":[166],"25%":[181],"penalties.":[184]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":6},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}