{"id":"https://openalex.org/W2169075236","doi":"https://doi.org/10.1109/tvlsi.2010.2060502","title":"On the Use of Simple Electrical Circuit Techniques for Performance Modeling and Optimization in VLSI Systems","display_name":"On the Use of Simple Electrical Circuit Techniques for Performance Modeling and Optimization in VLSI Systems","publication_year":2010,"publication_date":"2010-08-24","ids":{"openalex":"https://openalex.org/W2169075236","doi":"https://doi.org/10.1109/tvlsi.2010.2060502","mag":"2169075236"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2010.2060502","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2010.2060502","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072491367","display_name":"Gautam Hazari","orcid":null},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"G. Hazari","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110098941","display_name":"H. Narayanan","orcid":"https://orcid.org/0000-0002-9169-3425"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"H. Narayanan","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I162827531"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.22744294,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"19","issue":"10","first_page":"1861","last_page":"1873"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.8344202041625977},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7489132881164551},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5499564409255981},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.5089113712310791},{"id":"https://openalex.org/keywords/queueing-theory","display_name":"Queueing theory","score":0.46787258982658386},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.4304423928260803},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4295567274093628},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.41788333654403687},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.40214723348617554},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.34980618953704834},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.27812427282333374},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.252236008644104},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12252822518348694}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.8344202041625977},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7489132881164551},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5499564409255981},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.5089113712310791},{"id":"https://openalex.org/C22684755","wikidata":"https://www.wikidata.org/wiki/Q847526","display_name":"Queueing theory","level":2,"score":0.46787258982658386},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.4304423928260803},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4295567274093628},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.41788333654403687},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.40214723348617554},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.34980618953704834},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.27812427282333374},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.252236008644104},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12252822518348694},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2010.2060502","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2010.2060502","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":41,"referenced_works":["https://openalex.org/W1485627046","https://openalex.org/W1548168045","https://openalex.org/W1588799898","https://openalex.org/W1595273177","https://openalex.org/W1977545325","https://openalex.org/W1980082730","https://openalex.org/W1988544202","https://openalex.org/W1989841622","https://openalex.org/W1997145140","https://openalex.org/W1999650389","https://openalex.org/W2006800740","https://openalex.org/W2022740893","https://openalex.org/W2028951941","https://openalex.org/W2032598280","https://openalex.org/W2035720033","https://openalex.org/W2047462577","https://openalex.org/W2059807497","https://openalex.org/W2089155985","https://openalex.org/W2092608522","https://openalex.org/W2107026734","https://openalex.org/W2120080222","https://openalex.org/W2120209700","https://openalex.org/W2120244357","https://openalex.org/W2127142123","https://openalex.org/W2127548077","https://openalex.org/W2128728233","https://openalex.org/W2128904268","https://openalex.org/W2130156165","https://openalex.org/W2131578032","https://openalex.org/W2137078121","https://openalex.org/W2139745484","https://openalex.org/W2151937931","https://openalex.org/W2156149390","https://openalex.org/W2541139518","https://openalex.org/W2907740361","https://openalex.org/W3144433026","https://openalex.org/W4213060235","https://openalex.org/W4229823398","https://openalex.org/W6635230296","https://openalex.org/W6680924476","https://openalex.org/W6757937348"],"related_works":["https://openalex.org/W4283025278","https://openalex.org/W2082432309","https://openalex.org/W817174743","https://openalex.org/W2050492524","https://openalex.org/W2998315020","https://openalex.org/W2104790384","https://openalex.org/W1976665945","https://openalex.org/W3016208414","https://openalex.org/W2123642381","https://openalex.org/W2367494385"],"abstract_inverted_index":{"Leading-edge":[0],"VLSI":[1,102,190],"systems,":[2,191],"essentially":[3],"multiprocessor":[4],"systems-on-chip,":[5],"have":[6],"a":[7,97,118,164],"wide":[8],"range":[9],"of":[10,40,61,109,166,169],"components":[11],"integrated":[12],"together":[13],"and":[14,36,46,104,137,154,185,201],"operating":[15],"in":[16,25,58,133,140,174,189],"unison.":[17],"They":[18],"can":[19,193],"be":[20,66,195],"analyzed":[21],"as":[22,48,50,69,122,144,151],"flow":[23,57,85,188],"networks":[24,86],"which":[26,192],"the":[27,32,41,51,62,72,106,110,115,123,134,141,187],"system":[28,63],"performance":[29],"depends":[30],"on":[31],"bandwidth,":[33],"transmission":[34],"time,":[35],"queueing":[37],"delay":[38],"characteristics":[39],"individual":[42],"components,":[43],"their":[44],"connectivity":[45],"interactions,":[47],"well":[49],"traffic":[52],"patterns":[53],"they":[54],"encounter.":[55],"The":[56,157],"various":[59],"parts":[60],"must":[64],"ideally":[65],"distributed":[67],"so":[68],"to":[70,129,146],"extract":[71],"maximum":[73],"throughput":[74],"possible":[75],"with":[76],"minimum":[77],"end-to-end":[78],"delays.":[79],"Such":[80],"an":[81,180],"ideal":[82],"distribution":[83],"for":[84,100,183,204],"has":[87],"previously":[88],"been":[89],"obtained":[90],"using":[91,117],"simple":[92],"electrical":[93],"circuits.":[94],"We":[95,112,125],"demonstrate":[96],"similar":[98],"methodology":[99,116,128],"typical":[101],"systems":[103],"provide":[105],"necessary":[107],"extensions":[108],"theory.":[111],"empirically":[113],"validate":[114],"cycle-accurate":[119],"simulation":[120],"model":[121],"reference.":[124],"find":[126],"this":[127],"supply":[130],"better":[131],"distributions":[132,139],"average":[135],"case":[136,143],"comparable":[138],"worst":[142],"compared":[145],"standard":[147],"search":[148],"procedures":[149],"such":[150],"random":[152],"sampling":[153],"simulated":[155],"annealing.":[156],"real":[158],"strength":[159],"is":[160,179],"that":[161],"it":[162,178],"provides":[163],"speedup":[165],"several":[167],"orders":[168,173],"magnitude,":[170],"i.e.,":[171],"3-5":[172],"our":[175],"experiments.":[176],"Thus":[177],"elegant":[181],"means":[182],"analyzing":[184],"optimizing":[186],"easily":[194],"incorporated":[196],"into":[197],"design":[198],"procedures,":[199],"compilers":[200],"on-chip":[202],"modules":[203],"real-time":[205],"allocations.":[206]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
