{"id":"https://openalex.org/W2163793609","doi":"https://doi.org/10.1109/tvlsi.2010.2057265","title":"CROA: Design and Analysis of the Custom Rotary Oscillatory Array","display_name":"CROA: Design and Analysis of the Custom Rotary Oscillatory Array","publication_year":2010,"publication_date":"2010-08-24","ids":{"openalex":"https://openalex.org/W2163793609","doi":"https://doi.org/10.1109/tvlsi.2010.2057265","mag":"2163793609"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2010.2057265","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2010.2057265","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072530511","display_name":"Vinayak Honkote","orcid":null},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Vinayak Honkote","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I72816309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081080799","display_name":"Bar\u0131\u015f Ta\u015fk\u0131n","orcid":"https://orcid.org/0000-0002-7631-5696"},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Baris Taskin","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I72816309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5072530511"],"corresponding_institution_ids":["https://openalex.org/I72816309"],"apc_list":null,"apc_paid":null,"fwci":1.7318,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.86492279,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"19","issue":"10","first_page":"1837","last_page":"1847"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/partial-element-equivalent-circuit","display_name":"Partial element equivalent circuit","score":0.7769630551338196},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6048106551170349},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.5934454798698425},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.5681252479553223},{"id":"https://openalex.org/keywords/parasitic-extraction","display_name":"Parasitic extraction","score":0.5369320511817932},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.5127569437026978},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.479233056306839},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.47801029682159424},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.46273407340049744},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.36251354217529297},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.3275679051876068},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3024609088897705},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.2652170658111572},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.23884326219558716},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.11768367886543274},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09782171249389648}],"concepts":[{"id":"https://openalex.org/C2780328198","wikidata":"https://www.wikidata.org/wiki/Q2054492","display_name":"Partial element equivalent circuit","level":4,"score":0.7769630551338196},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6048106551170349},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.5934454798698425},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.5681252479553223},{"id":"https://openalex.org/C159818811","wikidata":"https://www.wikidata.org/wiki/Q7135947","display_name":"Parasitic extraction","level":2,"score":0.5369320511817932},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.5127569437026978},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.479233056306839},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.47801029682159424},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.46273407340049744},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.36251354217529297},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.3275679051876068},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3024609088897705},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.2652170658111572},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.23884326219558716},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.11768367886543274},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09782171249389648},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2010.2057265","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2010.2057265","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.49000000953674316,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1505272351","https://openalex.org/W1554301658","https://openalex.org/W1565658248","https://openalex.org/W1585683917","https://openalex.org/W1984845646","https://openalex.org/W1986100061","https://openalex.org/W1987083185","https://openalex.org/W1989105867","https://openalex.org/W2049078776","https://openalex.org/W2075891646","https://openalex.org/W2103168863","https://openalex.org/W2122724421","https://openalex.org/W2128060653","https://openalex.org/W2138857663","https://openalex.org/W2144402314","https://openalex.org/W2150547314","https://openalex.org/W2153580689","https://openalex.org/W2155670163","https://openalex.org/W2157488385","https://openalex.org/W2166694777","https://openalex.org/W3141822326","https://openalex.org/W4255697594","https://openalex.org/W6630124008","https://openalex.org/W6675471975","https://openalex.org/W6681419564"],"related_works":["https://openalex.org/W2087612346","https://openalex.org/W2164715378","https://openalex.org/W2144402314","https://openalex.org/W2136196184","https://openalex.org/W2144518356","https://openalex.org/W2128060653","https://openalex.org/W2075400577","https://openalex.org/W1933111433","https://openalex.org/W2121694082","https://openalex.org/W2112595964"],"abstract_inverted_index":{"Rotary":[0,19],"clocking":[1,5,20,29,44],"is":[2,69,96,102,171],"a":[3,37,49,62],"resonant":[4],"technology":[6,21],"for":[7,71],"clock":[8,33,169],"network":[9],"design":[10,100],"and":[11,74,87,146],"distribution":[12,75],"in":[13,118,152],"high":[14,31],"performance":[15],"digital":[16],"VLSI":[17],"circuits.":[18,109],"offers":[22],"an":[23],"attractive":[24],"alternative":[25],"to":[26,82,111,128,163,173],"the":[27,72,88,92,105,112,129,132,147,164,167,178,182,185,192],"conventional":[28],"with":[30,136,159],"frequency":[32,170,187],"signal":[34],"generation":[35,73],"at":[36],"low":[38],"power":[39],"dissipation":[40],"rate.":[41],"Traditionally,":[42],"rotary":[43,55,64,77,94],"has":[45],"been":[46],"implemented":[47],"using":[48],"regular":[50],"array":[51,66],"(grid)":[52],"topology":[53,68,133],"called":[54],"oscillatory":[56,65],"arrays":[57],"(ROA).":[58],"In":[59],"this":[60],"paper,":[61],"custom":[63,93,115],"(CROA)":[67],"proposed":[70],"of":[76,91,120,131,188],"clocking.":[78],"The":[79,98,124,154],"issues":[80],"related":[81],"timing":[83],"closure":[84],"are":[85,144,150],"addressed":[86],"simulation-based":[89],"analysis":[90,142],"rings":[95],"presented.":[97],"CROA":[99,148],"methodology":[101],"tested":[103],"on":[104],"IBM":[106],"R1-R5":[107],"benchmark":[108],"Compared":[110],"traditional":[113],"ROA,":[114],"ROA":[116],"results":[117,156],"39.25%":[119],"tapping":[121,179],"wirelength":[122,180],"savings.":[123],"parasitic":[125],"effects":[126],"due":[127,162],"customization":[130],"-":[134,143],"computed":[135],"partial":[137],"element":[138],"equivalent":[139],"circuit":[140],"(PEEC)":[141],"incorporated":[145],"topologies":[149],"simulated":[151],"SPICE.":[153],"simulation":[155],"show":[157],"that,":[158],"additional":[160],"parasitics":[161],"topological":[165,193],"factors,":[166],"resultant":[168],"observed":[172],"be":[174],"8.79%":[175],"slower":[176],"(assuming":[177],"remains":[181],"same)":[183],"than":[184],"expected":[186],"operation":[189],"without":[190],"considering":[191],"factors.":[194]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
