{"id":"https://openalex.org/W2185508384","doi":"https://doi.org/10.1109/tvlsi.2010.2052421","title":"Corrections to \u201cUnified Logical Effort\u2014A Method for Delay Evaluation and Minimization in Logic Paths With <i>RC</i> Interconnect\u201d [May 10 689-696]","display_name":"Corrections to \u201cUnified Logical Effort\u2014A Method for Delay Evaluation and Minimization in Logic Paths With <i>RC</i> Interconnect\u201d [May 10 689-696]","publication_year":2010,"publication_date":"2010-07-08","ids":{"openalex":"https://openalex.org/W2185508384","doi":"https://doi.org/10.1109/tvlsi.2010.2052421","mag":"2185508384"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2010.2052421","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2010.2052421","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034159041","display_name":"Arkadiy Morgenshtein","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104622","display_name":"Intel (Israel)","ror":"https://ror.org/027t2s119","country_code":"IL","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210104622"]},{"id":"https://openalex.org/I80687555","display_name":"Israel Electric (Israel)","ror":"https://ror.org/01p8dnv11","country_code":"IL","type":"company","lineage":["https://openalex.org/I80687555"]}],"countries":["IL"],"is_corresponding":true,"raw_author_name":"Arkadiy Morgenshtein","raw_affiliation_strings":["Core CAD Technologies Group, Intel Corporation, Haifa, Israel"],"affiliations":[{"raw_affiliation_string":"Core CAD Technologies Group, Intel Corporation, Haifa, Israel","institution_ids":["https://openalex.org/I80687555","https://openalex.org/I4210104622"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053517349","display_name":"Eby G. Friedman","orcid":"https://orcid.org/0000-0002-5549-7160"},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eby G. Friedman","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY, USA","institution_ids":["https://openalex.org/I5388228"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010407295","display_name":"Ran Ginosar","orcid":null},"institutions":[{"id":"https://openalex.org/I174306211","display_name":"Technion \u2013 Israel Institute of Technology","ror":"https://ror.org/03qryx823","country_code":"IL","type":"education","lineage":["https://openalex.org/I174306211"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Ran Ginosar","raw_affiliation_strings":["Department of Electrical Engineering, The Technion Israel Institute of Technology, Haifa, Israel"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, The Technion Israel Institute of Technology, Haifa, Israel","institution_ids":["https://openalex.org/I174306211"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051888366","display_name":"Avinoam Kolodny","orcid":null},"institutions":[{"id":"https://openalex.org/I174306211","display_name":"Technion \u2013 Israel Institute of Technology","ror":"https://ror.org/03qryx823","country_code":"IL","type":"education","lineage":["https://openalex.org/I174306211"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Avinoam Kolodny","raw_affiliation_strings":["Department of Electrical Engineering, The Technion Israel Institute of Technology, Haifa, Israel"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, The Technion Israel Institute of Technology, Haifa, Israel","institution_ids":["https://openalex.org/I174306211"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5034159041"],"corresponding_institution_ids":["https://openalex.org/I4210104622","https://openalex.org/I80687555"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.18155347,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"18","issue":"8","first_page":"1262","last_page":"1262"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.6731954216957092},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6112054586410522},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5545368790626526},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.47213178873062134},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4502434730529785},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.33217477798461914},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3083476424217224},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.17356818914413452},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.13369673490524292}],"concepts":[{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.6731954216957092},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6112054586410522},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5545368790626526},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.47213178873062134},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4502434730529785},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.33217477798461914},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3083476424217224},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.17356818914413452},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.13369673490524292}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2010.2052421","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2010.2052421","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W2109288479"],"related_works":["https://openalex.org/W2051487156","https://openalex.org/W2073681303","https://openalex.org/W2155019192","https://openalex.org/W2014709025","https://openalex.org/W4249035840","https://openalex.org/W2766970861","https://openalex.org/W3125341812","https://openalex.org/W1668171714","https://openalex.org/W4380607112","https://openalex.org/W2218294330"],"abstract_inverted_index":{"In":[0],"the":[1,14,17],"above":[2],"titled":[3],"paper":[4],"(ibid.,":[5],"vol.":[6],"18,":[7],"no.":[8],"5,":[9],"pp.":[10],"689-696,":[11],"May":[12],"10),":[13],"formula":[15],"and":[16],"caption":[18],"in":[19],"Fig.":[20],"3":[21],"appeared":[22],"incorrectly.":[23],"The":[24],"correct":[25],"figure":[26],"is":[27],"presented":[28],"here":[29],"along":[30],"with":[31],"an":[32],"explanation.":[33]},"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}
