{"id":"https://openalex.org/W2029663117","doi":"https://doi.org/10.1109/tvlsi.2010.2050500","title":"A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating","display_name":"A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating","publication_year":2010,"publication_date":"2010-06-16","ids":{"openalex":"https://openalex.org/W2029663117","doi":"https://doi.org/10.1109/tvlsi.2010.2050500","mag":"2029663117"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2010.2050500","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2010.2050500","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102097711","display_name":"Shota Ishihara","orcid":null},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shota Ishihara","raw_affiliation_strings":["Graduate School of Information Sciences, University of Tohoku, Sendai, Miyagi, Japan","Grad. Sch. of Inf. Sci., Tohoku Univ., Miyagi, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information Sciences, University of Tohoku, Sendai, Miyagi, Japan","institution_ids":["https://openalex.org/I201537933"]},{"raw_affiliation_string":"Grad. Sch. of Inf. Sci., Tohoku Univ., Miyagi, Japan","institution_ids":["https://openalex.org/I201537933"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070647966","display_name":"Masanori Hariyama","orcid":"https://orcid.org/0000-0002-1464-8807"},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masanori Hariyama","raw_affiliation_strings":["Graduate School of Information Sciences, University of Tohoku, Sendai, Miyagi, Japan","Grad. Sch. of Inf. Sci., Tohoku Univ., Miyagi, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information Sciences, University of Tohoku, Sendai, Miyagi, Japan","institution_ids":["https://openalex.org/I201537933"]},{"raw_affiliation_string":"Grad. Sch. of Inf. Sci., Tohoku Univ., Miyagi, Japan","institution_ids":["https://openalex.org/I201537933"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037191455","display_name":"Michitaka Kameyama","orcid":"https://orcid.org/0000-0002-4245-9907"},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Michitaka Kameyama","raw_affiliation_strings":["Graduate School of Information Sciences, University of Tohoku, Sendai, Miyagi, Japan","Grad. Sch. of Inf. Sci., Tohoku Univ., Miyagi, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information Sciences, University of Tohoku, Sendai, Miyagi, Japan","institution_ids":["https://openalex.org/I201537933"]},{"raw_affiliation_string":"Grad. Sch. of Inf. Sci., Tohoku Univ., Miyagi, Japan","institution_ids":["https://openalex.org/I201537933"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I201537933"],"apc_list":null,"apc_paid":null,"fwci":3.477,"has_fulltext":false,"cited_by_count":50,"citation_normalized_percentile":{"value":0.92671688,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"19","issue":"8","first_page":"1394","last_page":"1406"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.8883846998214722},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7909953594207764},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7338066697120667},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.728553295135498},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.4416770040988922},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.43419256806373596},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4336886703968048},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42653828859329224},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41442665457725525},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.20728662610054016},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19131940603256226},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.17570388317108154},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.126297265291214}],"concepts":[{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.8883846998214722},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7909953594207764},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7338066697120667},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.728553295135498},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.4416770040988922},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.43419256806373596},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4336886703968048},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42653828859329224},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41442665457725525},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.20728662610054016},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19131940603256226},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.17570388317108154},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.126297265291214},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2010.2050500","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2010.2050500","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8899999856948853,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":41,"referenced_works":["https://openalex.org/W178228768","https://openalex.org/W1505010091","https://openalex.org/W1561252668","https://openalex.org/W1582019256","https://openalex.org/W1604816148","https://openalex.org/W1769133684","https://openalex.org/W1928299412","https://openalex.org/W2001824086","https://openalex.org/W2006097283","https://openalex.org/W2016228603","https://openalex.org/W2016748970","https://openalex.org/W2029663117","https://openalex.org/W2050848724","https://openalex.org/W2055739500","https://openalex.org/W2091206994","https://openalex.org/W2097717709","https://openalex.org/W2102121056","https://openalex.org/W2121797451","https://openalex.org/W2121826101","https://openalex.org/W2123654193","https://openalex.org/W2128723913","https://openalex.org/W2131862714","https://openalex.org/W2137769675","https://openalex.org/W2139791192","https://openalex.org/W2141841284","https://openalex.org/W2147191452","https://openalex.org/W2150667885","https://openalex.org/W2150872535","https://openalex.org/W2152001712","https://openalex.org/W2153478340","https://openalex.org/W2153793450","https://openalex.org/W2157847583","https://openalex.org/W2158899676","https://openalex.org/W2167971065","https://openalex.org/W2487142227","https://openalex.org/W2542455931","https://openalex.org/W6607265297","https://openalex.org/W6630127071","https://openalex.org/W6633384124","https://openalex.org/W6638190992","https://openalex.org/W6675231329"],"related_works":["https://openalex.org/W2138099459","https://openalex.org/W2031449089","https://openalex.org/W2112596406","https://openalex.org/W2259094912","https://openalex.org/W2024574431","https://openalex.org/W2117300767","https://openalex.org/W2374017528","https://openalex.org/W4285503609","https://openalex.org/W2126248441","https://openalex.org/W2371329481"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,76,83,133,141],"field-programmable":[4],"gate":[5],"array":[6],"(FPGA)":[7],"based":[8],"on":[9],"lookup":[10,88],"table":[11],"level":[12],"fine-grain":[13],"power":[14,20,58,62,66,149,152],"gating":[15,21,67],"with":[16,101],"small":[17,70,134],"overheads.":[18],"The":[19,90],"technique":[22,68],"implemented":[23],"in":[24,48],"the":[25,31,45,51,57,65,72,96,117,125,151],"proposed":[26,91,118],"architecture":[27],"can":[28],"directly":[29],"detect":[30],"activity":[32],"of":[33,40,60,75],"each":[34],"look-up-table":[35],"easily":[36],"by":[37,157],"exploiting":[38],"features":[39],"asynchronous":[41,146],"architectures.":[42],"Moreover,":[43],"detecting":[44],"data":[46],"arrival":[47],"advance":[49],"prevents":[50],"delay":[52],"increase":[53],"for":[54,114,122],"waking-up":[55],"and":[56,86,144,159],"consumption":[59,153],"unnecessary":[61],"switching.":[63],"Since":[64,116],"has":[69],"overheads,":[71],"granularity":[73],"size":[74],"power-gated":[77],"domain":[78],"is":[79,93,120,137,154],"as":[80,82],"fine":[81],"single":[84],"two-input":[85],"one-output":[87],"table.":[89],"FPGA":[92,119,143,147],"fabricated":[94],"using":[95],"ASPLA":[97],"90-nm":[98],"CMOS":[99],"process":[100],"dual":[102],"threshold":[103],"voltages.":[104],"We":[105],"use":[106],"an":[107,129,145],"image":[108],"processing":[109,123],"application":[110],"called":[111],"\u201ctemplate":[112],"matching\u201d":[113],"evaluation.":[115],"suitable":[121],"where":[124,132],"workload":[126],"changes":[127],"dynamically,":[128],"adaptive":[130],"algorithm":[131],"computational":[135],"kernel":[136],"employed.":[138],"Compared":[139],"to":[140],"synchronous":[142],"without":[148],"gating,":[150],"reduced":[155],"respectively":[156],"38%":[158],"15%":[160],"at":[161],"85\u00b0C.":[162]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":9},{"year":2013,"cited_by_count":6},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}