{"id":"https://openalex.org/W2096263144","doi":"https://doi.org/10.1109/tvlsi.2010.2048588","title":"CVNS-Based Storage and Refreshing Scheme for a Multi-Valued Dynamic Memory","display_name":"CVNS-Based Storage and Refreshing Scheme for a Multi-Valued Dynamic Memory","publication_year":2010,"publication_date":"2010-05-21","ids":{"openalex":"https://openalex.org/W2096263144","doi":"https://doi.org/10.1109/tvlsi.2010.2048588","mag":"2096263144"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2010.2048588","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2010.2048588","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020042387","display_name":"Golnar Khodabandehloo","orcid":null},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Golnar Khodabandehloo","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Windsor, Windsor, ONT, Canada","Dept. of Electr. & Comput. Eng, Univ. of Windsor, Windsor, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Windsor, Windsor, ONT, Canada","institution_ids":["https://openalex.org/I74413500"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, Univ. of Windsor, Windsor, ON, Canada","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042170452","display_name":"Mitra Mirhassani","orcid":"https://orcid.org/0000-0001-8512-6427"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Mitra Mirhassani","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Windsor, Windsor, ONT, Canada","Dept. of Electr. & Comput. Eng, Univ. of Windsor, Windsor, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Windsor, Windsor, ONT, Canada","institution_ids":["https://openalex.org/I74413500"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, Univ. of Windsor, Windsor, ON, Canada","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5116239815","display_name":"Majid Ahmadi","orcid":"https://orcid.org/0009-0006-4046-2121"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Majid Ahmadi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Windsor, Windsor, ONT, Canada","Dept. of Electr. & Comput. Eng, Univ. of Windsor, Windsor, ON, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Windsor, Windsor, ONT, Canada","institution_ids":["https://openalex.org/I74413500"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, Univ. of Windsor, Windsor, ON, Canada","institution_ids":["https://openalex.org/I74413500"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5020042387"],"corresponding_institution_ids":["https://openalex.org/I74413500"],"apc_list":null,"apc_paid":null,"fwci":1.3381,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.81342417,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"19","issue":"8","first_page":"1517","last_page":"1521"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10682","display_name":"Quantum Computing Algorithms and Architecture","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/noise-margin","display_name":"Noise margin","score":0.6906988620758057},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6808719635009766},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.6041861772537231},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5727444887161255},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5721158981323242},{"id":"https://openalex.org/keywords/computer-data-storage","display_name":"Computer data storage","score":0.56380295753479},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5407424569129944},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.4633605480194092},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.45586255192756653},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.45094916224479675},{"id":"https://openalex.org/keywords/margin","display_name":"Margin (machine learning)","score":0.4288630485534668},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.33132490515708923},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3200734853744507},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2968628406524658},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.2629290819168091},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20115268230438232},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.14746609330177307},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10470712184906006},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10330244898796082},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.09606915712356567}],"concepts":[{"id":"https://openalex.org/C179499742","wikidata":"https://www.wikidata.org/wiki/Q1324892","display_name":"Noise margin","level":4,"score":0.6906988620758057},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6808719635009766},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.6041861772537231},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5727444887161255},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5721158981323242},{"id":"https://openalex.org/C194739806","wikidata":"https://www.wikidata.org/wiki/Q66221","display_name":"Computer data storage","level":2,"score":0.56380295753479},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5407424569129944},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.4633605480194092},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.45586255192756653},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.45094916224479675},{"id":"https://openalex.org/C774472","wikidata":"https://www.wikidata.org/wiki/Q6760393","display_name":"Margin (machine learning)","level":2,"score":0.4288630485534668},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.33132490515708923},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3200734853744507},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2968628406524658},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.2629290819168091},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20115268230438232},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.14746609330177307},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10470712184906006},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10330244898796082},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09606915712356567},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2010.2048588","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2010.2048588","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.699999988079071,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1730322892","https://openalex.org/W1869040355","https://openalex.org/W1997159982","https://openalex.org/W2086594390","https://openalex.org/W2103139761","https://openalex.org/W2106399682","https://openalex.org/W2128140661","https://openalex.org/W2134034341","https://openalex.org/W2134438536","https://openalex.org/W2154176871","https://openalex.org/W2157819700","https://openalex.org/W2158800590","https://openalex.org/W2167182882","https://openalex.org/W2169907848"],"related_works":["https://openalex.org/W3125011624","https://openalex.org/W1508631387","https://openalex.org/W2370917603","https://openalex.org/W2017776670","https://openalex.org/W2952760143","https://openalex.org/W2154145758","https://openalex.org/W2110839220","https://openalex.org/W2096263144","https://openalex.org/W2103139761","https://openalex.org/W3214912654"],"abstract_inverted_index":{"Multi-valued":[0],"dynamic":[1,47],"memories":[2],"are":[3,96],"appropriate":[4],"for":[5],"applications":[6],"such":[7],"as":[8],"implementation":[9],"of":[10,16,79],"neural":[11],"networks,":[12],"where":[13],"massive":[14],"number":[15],"synaptic":[17],"weights":[18],"have":[19],"to":[20,35,38,66,74],"be":[21],"stored":[22],"on":[23,45,55],"a":[24,29,46],"chip.":[25],"In":[26],"this":[27],"paper,":[28],"novel":[30],"storage":[31],"and":[32,99],"refreshing":[33],"configuration":[34,52],"store":[36],"up":[37],"4":[39],"bits":[40],"(16":[41],"levels)":[42],"per":[43],"cell":[44],"memory":[48,80],"is":[49,53,70,92],"proposed.":[50],"This":[51],"based":[54],"the":[56,67,76,85,88],"Continuous":[57],"Valued":[58],"Number":[59],"System":[60],"(CVNS).":[61],"Error":[62],"correction":[63],"method":[64],"according":[65],"CVNS":[68],"properties":[69],"used":[71],"in":[72],"order":[73],"increase":[75],"noise":[77],"margin":[78],"cells.":[81],"Furthermore,":[82],"by":[83],"decreasing":[84],"leakage":[86],"current,":[87],"refresh":[89],"cycle":[90],"time":[91],"increased.":[93],"The":[94],"circuits":[95],"designed,":[97],"simulated,":[98],"finally":[100],"laid":[101],"out":[102],"using":[103],"90-nm":[104],"CMOS":[105],"technology.":[106]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}