{"id":"https://openalex.org/W2132250356","doi":"https://doi.org/10.1109/tvlsi.2010.2042184","title":"An Enhanced Canary-Based System With BIST for SRAM Standby Power Reduction","display_name":"An Enhanced Canary-Based System With BIST for SRAM Standby Power Reduction","publication_year":2010,"publication_date":"2010-03-12","ids":{"openalex":"https://openalex.org/W2132250356","doi":"https://doi.org/10.1109/tvlsi.2010.2042184","mag":"2132250356"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2010.2042184","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2010.2042184","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Jiajing Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jiajing Wang","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","[Dept. of Electr. & Comput. Eng., Univ. of Virginia, Charlottesville, VA, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Univ. of Virginia, Charlottesville, VA, USA]","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069769007","display_name":"Alexander Hoefler","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Alexander Hoefler","raw_affiliation_strings":["Freescale Semiconductor, Inc., Austin, TX, USA",", Freescale Semiconductor, Austin, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Inc., Austin, TX, USA","institution_ids":[]},{"raw_affiliation_string":", Freescale Semiconductor, Austin, TX, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080557997","display_name":"Benton H. Calhoun","orcid":"https://orcid.org/0000-0002-3770-5050"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Benton H. Calhoun","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","[Dept. of Electr. & Comput. Eng., Univ. of Virginia, Charlottesville, VA, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Univ. of Virginia, Charlottesville, VA, USA]","institution_ids":["https://openalex.org/I51556381"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2897,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.65624056,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"19","issue":"5","first_page":"909","last_page":"914"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7861378192901611},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5283499360084534},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5258482098579407},{"id":"https://openalex.org/keywords/standby-power","display_name":"Standby power","score":0.4703510105609894},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4665628969669342},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4623033106327057},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.39378154277801514},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3235020041465759},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3207259178161621},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.23633116483688354},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22732290625572205},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.11891192197799683},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11883613467216492}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7861378192901611},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5283499360084534},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5258482098579407},{"id":"https://openalex.org/C7140552","wikidata":"https://www.wikidata.org/wiki/Q1366402","display_name":"Standby power","level":3,"score":0.4703510105609894},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4665628969669342},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4623033106327057},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.39378154277801514},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3235020041465759},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3207259178161621},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.23633116483688354},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22732290625572205},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.11891192197799683},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11883613467216492},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2010.2042184","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2010.2042184","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1966298615","https://openalex.org/W1968597908","https://openalex.org/W2099569060","https://openalex.org/W2109458212","https://openalex.org/W2126221193","https://openalex.org/W2127485220","https://openalex.org/W2131054871","https://openalex.org/W2154941994","https://openalex.org/W4248310916","https://openalex.org/W6676534250"],"related_works":["https://openalex.org/W2321291171","https://openalex.org/W3151633427","https://openalex.org/W2140159669","https://openalex.org/W2773448237","https://openalex.org/W2188598220","https://openalex.org/W2162271340","https://openalex.org/W2119025037","https://openalex.org/W2894040387","https://openalex.org/W2539500217","https://openalex.org/W4377020067"],"abstract_inverted_index":{"To":[0],"achieve":[1],"aggressive":[2],"standby":[3,96],"power":[4],"reduction":[5],"for":[6,46],"static":[7],"random":[8],"access":[9],"memory":[10],"(SRAM),":[11],"we":[12,35],"have":[13],"previously":[14],"proposed":[15],"a":[16,71,114],"closed-loop":[17],"V":[18],"<sub":[19,100],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[20,98,101],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">DD</sub>":[21,102],"scaling":[22],"system":[23,45],"with":[24],"canary":[25,55,65,72,126,142],"replicas":[26],"that":[27,70,133],"can":[28],"track":[29],"global":[30],"variations.":[31,62],"In":[32],"this":[33,44],"paper,":[34],"propose":[36],"several":[37],"techniques":[38],"to":[39,109],"enhance":[40],"the":[41,54,58,68,104,122,125,138,141],"efficiency":[42],"of":[43,60,93,124,140],"more":[47,82],"advanced":[48],"technologies.":[49],"Adding":[50],"dummy":[51,135],"cells":[52,127,136],"around":[53],"cell":[56,73],"improves":[57],"tracking":[59],"systematic":[61],"A":[63,86],"new":[64,115],"circuit":[66],"avoids":[67],"possibility":[69],"may":[74],"never":[75],"fail":[76],"because":[77],"it":[78],"resets":[79],"into":[80],"its":[81],"stable":[83],"data":[84],"pattern.":[85],"built-in":[87],"self-test":[88],"(BIST)":[89],"block":[90],"incorporates":[91],"self-calibration":[92],"SRAM":[94],"minimum":[95],"<i":[97],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">V</i>":[99],"and":[103,131],"initial":[105],"failure":[106],"threshold":[107],"due":[108],"intrinsic":[110],"mismatch.":[111],"Measurements":[112],"from":[113],"45":[116],"nm":[117],"test":[118],"chip":[119],"further":[120],"demonstrate":[121],"function":[123],"in":[128],"smaller":[129],"technology":[130],"show":[132],"adding":[134],"reduces":[137],"variation":[139],"cell.":[143]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2014,"cited_by_count":4},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
