{"id":"https://openalex.org/W2134407795","doi":"https://doi.org/10.1109/tvlsi.2009.2037910","title":"A Synchronous 50% Duty-Cycle Clock Generator in 0.35-$\\mu$m CMOS","display_name":"A Synchronous 50% Duty-Cycle Clock Generator in 0.35-$\\mu$m CMOS","publication_year":2010,"publication_date":"2010-01-12","ids":{"openalex":"https://openalex.org/W2134407795","doi":"https://doi.org/10.1109/tvlsi.2009.2037910","mag":"2134407795"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2009.2037910","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2037910","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027314134","display_name":"Tsung\u2010Hsien Lin","orcid":"https://orcid.org/0000-0002-1733-5945"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Tsung-Hsien Lin","raw_affiliation_strings":["Graduate Institute of Electronics Engineering and the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","Dept. of Electr. Eng.. Nat. Taiwan Univ., Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering and the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Dept. of Electr. Eng.. Nat. Taiwan Univ., Taipei, Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066626437","display_name":"Chao-Ching Chi","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chao-Ching Chi","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan#TAB#"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan#TAB#","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113910295","display_name":"Wei-Hao Chiu","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wei-Hao Chiu","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan#TAB#"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan#TAB#","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048096590","display_name":"Yu-Hsiang Huang","orcid":"https://orcid.org/0000-0001-8162-7806"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yu-Hsiang Huang","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan#TAB#"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan#TAB#","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5027314134"],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":2.3091,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.89286606,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"19","issue":"4","first_page":"585","last_page":"591"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.8257156014442444},{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.77716064453125},{"id":"https://openalex.org/keywords/integrator","display_name":"Integrator","score":0.7655247449874878},{"id":"https://openalex.org/keywords/signal-edge","display_name":"Signal edge","score":0.5716425776481628},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5702504515647888},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.5530105233192444},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.5136272311210632},{"id":"https://openalex.org/keywords/signal-generator","display_name":"Signal generator","score":0.4677942395210266},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.46337857842445374},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.45427852869033813},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4398549795150757},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.421560674905777},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41798728704452515},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.39816099405288696},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.32726359367370605},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3012380003929138},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.2704222798347473},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.18806344270706177},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.12958505749702454},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.11512964963912964},{"id":"https://openalex.org/keywords/analog-signal","display_name":"Analog signal","score":0.07149922847747803}],"concepts":[{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.8257156014442444},{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.77716064453125},{"id":"https://openalex.org/C79518650","wikidata":"https://www.wikidata.org/wiki/Q2081431","display_name":"Integrator","level":3,"score":0.7655247449874878},{"id":"https://openalex.org/C117525741","wikidata":"https://www.wikidata.org/wiki/Q775654","display_name":"Signal edge","level":4,"score":0.5716425776481628},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5702504515647888},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.5530105233192444},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.5136272311210632},{"id":"https://openalex.org/C207912722","wikidata":"https://www.wikidata.org/wiki/Q1259123","display_name":"Signal generator","level":3,"score":0.4677942395210266},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.46337857842445374},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.45427852869033813},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4398549795150757},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.421560674905777},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41798728704452515},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.39816099405288696},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.32726359367370605},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3012380003929138},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2704222798347473},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.18806344270706177},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.12958505749702454},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.11512964963912964},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.07149922847747803},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2009.2037910","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2037910","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.7200000286102295,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320329714","display_name":"Dutch Colorectal Cancer Group","ror":"https://ror.org/00nsb1162"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1558158353","https://openalex.org/W1925667094","https://openalex.org/W1974462868","https://openalex.org/W1993992280","https://openalex.org/W2029108875","https://openalex.org/W2070555782","https://openalex.org/W2082715750","https://openalex.org/W2092075230","https://openalex.org/W2108537242","https://openalex.org/W2130156225","https://openalex.org/W2133210053","https://openalex.org/W2146423999","https://openalex.org/W2161518222","https://openalex.org/W2340429540","https://openalex.org/W2542472824","https://openalex.org/W2747041610","https://openalex.org/W6640183248","https://openalex.org/W6673541384"],"related_works":["https://openalex.org/W4232628459","https://openalex.org/W1572462408","https://openalex.org/W2052455055","https://openalex.org/W2090237663","https://openalex.org/W2125901692","https://openalex.org/W4386292891","https://openalex.org/W2169622190","https://openalex.org/W2151256709","https://openalex.org/W2134407795","https://openalex.org/W2154337543"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,16,20,43,108,123,148],"synchronous":[4],"50%":[5],"duty-cycle":[6,136],"clock":[7,17,25],"generator":[8,18,26],"(DCCG).":[9],"The":[10,24,46,67,102,112,135],"proposed":[11,68,103],"DCCG":[12,69,104],"circuit":[13,113,153],"comprises":[14],"of":[15,126,138],"and":[19,64,83,93,121],"phase":[21,53,59,76],"error":[22,54,77,137],"integrator.":[23],"is":[27,40,49,70,78,90,105,142],"edge-triggered":[28],"by":[29,42,51],"an":[30,35],"input":[31,63,82,127],"signal":[32,96,141],"to":[33,100,118,133],"produce":[34],"output":[36,65,84,95,140],"whose":[37],"pulse":[38],"width":[39],"determined":[41],"delay":[44,47,89],"line.":[45],"line":[48],"controlled":[50],"the":[52,58,62,75,81,88,94,139],"integrator":[55],"which":[56],"detects":[57],"difference":[60],"between":[61],"signals.":[66],"designed":[71],"such":[72],"that":[73],"when":[74],"zeroed,":[79],"i.e.,":[80],"signals":[85],"are":[86],"synchronized,":[87],"properly":[91],"adjusted":[92],"duty":[97,128],"cycle":[98,129],"converges":[99],"50%.":[101],"implemented":[106],"in":[107],"0.35-\u03bcm":[109],"CMOS":[110],"process.":[111],"can":[114],"operate":[115],"from":[116,131,147],"70":[117],"500":[119,158],"MHz,":[120],"accommodates":[122],"wide":[124],"range":[125],"ranging":[130],"5%":[132],"95%.":[134],"less":[143],"than":[144],"1.5%.":[145],"Operated":[146],"3.3-V":[149],"supply":[150],"voltage,":[151],"this":[152],"dissipates":[154],"7":[155],"mA":[156],"at":[157],"MHz.":[159]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}