{"id":"https://openalex.org/W2108453702","doi":"https://doi.org/10.1109/tvlsi.2009.2035509","title":"Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM)","display_name":"Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM)","publication_year":2009,"publication_date":"2009-12-11","ids":{"openalex":"https://openalex.org/W2108453702","doi":"https://doi.org/10.1109/tvlsi.2009.2035509","mag":"2108453702"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2009.2035509","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2035509","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5013867024","display_name":"Wei Xu","orcid":"https://orcid.org/0000-0001-9341-8382"},"institutions":[{"id":"https://openalex.org/I165799507","display_name":"Rensselaer Polytechnic Institute","ror":"https://ror.org/01rtyzb94","country_code":"US","type":"education","lineage":["https://openalex.org/I165799507"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wei Xu","raw_affiliation_strings":["Electrical and Computer Science Engineering (ECSE) Department, Rensselaer Polytechnic Institute, Troy, NY, USA","Electr. & Comput. Sci. Engi neering (ECSE) Dept., Rensselaer Polytech. Inst., Troy, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Science Engineering (ECSE) Department, Rensselaer Polytechnic Institute, Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]},{"raw_affiliation_string":"Electr. & Comput. Sci. Engi neering (ECSE) Dept., Rensselaer Polytech. Inst., Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100706029","display_name":"Hongbin Sun","orcid":"https://orcid.org/0000-0003-2153-2906"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hongbin Sun","raw_affiliation_strings":["Institute of AI&R, Xi'an Jiaotong University, Xi'an, Shaanxi, China","Institute of AI&R, Xi'an Jiaotong University, Xi'an, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of AI&R, Xi'an Jiaotong University, Xi'an, Shaanxi, China","institution_ids":["https://openalex.org/I87445476"]},{"raw_affiliation_string":"Institute of AI&R, Xi'an Jiaotong University, Xi'an, China","institution_ids":["https://openalex.org/I87445476"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036254084","display_name":"Xiaobin Wang","orcid":"https://orcid.org/0000-0003-0606-4710"},"institutions":[{"id":"https://openalex.org/I131787340","display_name":"Seagate (United States)","ror":"https://ror.org/04p1xtv71","country_code":"US","type":"company","lineage":["https://openalex.org/I131787340"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiaobin Wang","raw_affiliation_strings":["Seagate Technologies, Inc., Bloomington, MN, USA",", Seagate Technology, Bloomington, MN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Seagate Technologies, Inc., Bloomington, MN, USA","institution_ids":["https://openalex.org/I131787340"]},{"raw_affiliation_string":", Seagate Technology, Bloomington, MN, USA","institution_ids":["https://openalex.org/I131787340"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058073627","display_name":"Yiran Chen","orcid":"https://orcid.org/0000-0002-1486-8412"},"institutions":[{"id":"https://openalex.org/I131787340","display_name":"Seagate (United States)","ror":"https://ror.org/04p1xtv71","country_code":"US","type":"company","lineage":["https://openalex.org/I131787340"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yiran Chen","raw_affiliation_strings":["Seagate Technologies, Inc., Bloomington, MN, USA",", Seagate Technology, Bloomington, MN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Seagate Technologies, Inc., Bloomington, MN, USA","institution_ids":["https://openalex.org/I131787340"]},{"raw_affiliation_string":", Seagate Technology, Bloomington, MN, USA","institution_ids":["https://openalex.org/I131787340"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100378796","display_name":"Tong Zhang","orcid":"https://orcid.org/0000-0002-6434-0712"},"institutions":[{"id":"https://openalex.org/I165799507","display_name":"Rensselaer Polytechnic Institute","ror":"https://ror.org/01rtyzb94","country_code":"US","type":"education","lineage":["https://openalex.org/I165799507"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tong Zhang","raw_affiliation_strings":["Electrical and Computer Science Engineering (ECSE) Department, Rensselaer Polytechnic Institute, Troy, NY, USA","Electr. & Comput. Sci. Engi neering (ECSE) Dept., Rensselaer Polytech. Inst., Troy, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Science Engineering (ECSE) Department, Rensselaer Polytechnic Institute, Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]},{"raw_affiliation_string":"Electr. & Comput. Sci. Engi neering (ECSE) Dept., Rensselaer Polytech. Inst., Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.5459,"has_fulltext":false,"cited_by_count":137,"citation_normalized_percentile":{"value":0.95280104,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":95,"max":100},"biblio":{"volume":"19","issue":"3","first_page":"483","last_page":"493"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10049","display_name":"Magnetic properties of thin films","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/3107","display_name":"Atomic and Molecular Physics, and Optics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10049","display_name":"Magnetic properties of thin films","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/3107","display_name":"Atomic and Molecular Physics, and Optics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7387198805809021},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6453820466995239},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6379368305206299},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.5454398989677429},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.5270110368728638},{"id":"https://openalex.org/keywords/non-uniform-memory-access","display_name":"Non-uniform memory access","score":0.5211701393127441},{"id":"https://openalex.org/keywords/spin-transfer-torque","display_name":"Spin-transfer torque","score":0.5160474181175232},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.51141756772995},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4742523729801178},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.4653722941875458},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.46156516671180725},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.42689383029937744},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.37393274903297424},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.31122303009033203},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3069961369037628},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.2868502140045166},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1252608299255371}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7387198805809021},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6453820466995239},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6379368305206299},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.5454398989677429},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.5270110368728638},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.5211701393127441},{"id":"https://openalex.org/C609986","wikidata":"https://www.wikidata.org/wiki/Q844840","display_name":"Spin-transfer torque","level":4,"score":0.5160474181175232},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.51141756772995},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4742523729801178},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.4653722941875458},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.46156516671180725},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.42689383029937744},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.37393274903297424},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.31122303009033203},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3069961369037628},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.2868502140045166},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1252608299255371},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C32546565","wikidata":"https://www.wikidata.org/wiki/Q856711","display_name":"Magnetization","level":3,"score":0.0},{"id":"https://openalex.org/C115260700","wikidata":"https://www.wikidata.org/wiki/Q11408","display_name":"Magnetic field","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2009.2035509","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2035509","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.9100000262260437}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W2008904077","https://openalex.org/W2025550430","https://openalex.org/W2042076387","https://openalex.org/W2046550312","https://openalex.org/W2053445801","https://openalex.org/W2075769654","https://openalex.org/W2081816493","https://openalex.org/W2096470311","https://openalex.org/W2102840382","https://openalex.org/W2118811056","https://openalex.org/W2122385695","https://openalex.org/W2128767249","https://openalex.org/W2148394909","https://openalex.org/W2148831941","https://openalex.org/W2151805400","https://openalex.org/W2153456949","https://openalex.org/W2155990326","https://openalex.org/W2157922084","https://openalex.org/W2543205889","https://openalex.org/W3147370038","https://openalex.org/W4238514142","https://openalex.org/W6652408048","https://openalex.org/W6677824804","https://openalex.org/W6682987294"],"related_works":["https://openalex.org/W1598433531","https://openalex.org/W3108993429","https://openalex.org/W126098351","https://openalex.org/W4229967581","https://openalex.org/W2047684617","https://openalex.org/W2021929420","https://openalex.org/W2007929622","https://openalex.org/W254684032","https://openalex.org/W2998091606","https://openalex.org/W2183575955"],"abstract_inverted_index":{"Because":[0],"of":[1,49,141,182],"its":[2,50],"high":[3,14],"storage":[4,51],"density":[5],"with":[6,129],"superior":[7],"scalability,":[8],"low":[9],"integration":[10],"cost":[11],"and":[12,95,153],"reasonably":[13],"access":[15,20],"speed,":[16],"spin-torque":[17],"transfer":[18],"random":[19],"memory":[21,75,85,106,132,151],"(STT":[22],"RAM)":[23],"appears":[24],"to":[25,30,45,62,177],"have":[26,102],"a":[27,63,138,180],"promising":[28],"potential":[29],"replace":[31],"SRAM":[32],"as":[33],"last-level":[34],"on-chip":[35],"cache":[36,128,172],"(e.g.,":[37],"L2":[38],"or":[39],"L3":[40],"cache)":[41],"for":[42],"microprocessors.":[43],"Due":[44],"unique":[46],"operational":[47],"characteristics":[48],"device":[52,111],"magnetic":[53],"tunneling":[54],"junction":[55],"(MTJ),":[56],"STT":[57,118,126,170],"RAM":[58,119,127,171],"is":[59,71],"inherently":[60],"subject":[61],"write":[64],"latency":[65,68],"versus":[66],"read":[67],"tradeoff":[69],"that":[70,97,123,163],"determined":[72],"by":[73,175],"the":[74,90],"cell":[76,86,107,133],"size.":[77],"This":[78,144],"paper":[79],"first":[80],"quantitatively":[81],"studies":[82],"how":[83],"different":[84,98],"sizing":[87],"may":[88,101],"impact":[89],"overall":[91],"computing":[92,99,142,154],"system":[93,155],"performance,":[94],"shows":[96],"workloads":[100],"conflicting":[103],"expectations":[104],"on":[105],"sizing.":[108],"Leveraging":[109],"MTJ":[110],"switching":[112],"characteristics,":[113],"we":[114,161],"further":[115],"propose":[116],"an":[117],"architecture":[120],"design":[121,165],"method":[122,166],"can":[124,167],"make":[125],"relatively":[130],"small":[131],"size":[134],"perform":[135],"well":[136,147],"over":[137,179],"wide":[139],"spectrum":[140],"benchmarks.":[143,183],"has":[145],"been":[146],"demonstrated":[148],"using":[149,158],"CACTI-based":[150],"modeling":[152],"performance":[156],"simulations":[157],"SimpleScalar.":[159],"Moreover,":[160],"show":[162],"this":[164],"also":[168],"reduce":[169],"energy":[173],"consumption":[174],"up":[176],"30%":[178],"variety":[181]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":7},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":9},{"year":2018,"cited_by_count":6},{"year":2017,"cited_by_count":17},{"year":2016,"cited_by_count":13},{"year":2015,"cited_by_count":16},{"year":2014,"cited_by_count":18},{"year":2013,"cited_by_count":15},{"year":2012,"cited_by_count":14}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
