{"id":"https://openalex.org/W2156891695","doi":"https://doi.org/10.1109/tvlsi.2009.2035322","title":"On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals","display_name":"On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals","publication_year":2009,"publication_date":"2009-11-23","ids":{"openalex":"https://openalex.org/W2156891695","doi":"https://doi.org/10.1109/tvlsi.2009.2035322","mag":"2156891695"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2009.2035322","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2035322","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100450742","display_name":"Ling Zhang","orcid":"https://orcid.org/0000-0002-4881-3989"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ling Zhang","raw_affiliation_strings":["Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101931324","display_name":"Yulei Zhang","orcid":"https://orcid.org/0000-0002-7055-9227"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yulei Zhang","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California, San Diego, La Jolla, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California, San Diego, La Jolla, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5115601812","display_name":"Hongyu Chen","orcid":"https://orcid.org/0000-0002-5325-9249"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hongyu Chen","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California, San Diego, La Jolla, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California, San Diego, La Jolla, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025550960","display_name":"Bo Yao","orcid":"https://orcid.org/0009-0002-2225-9956"},"institutions":[{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bo Yao","raw_affiliation_strings":["Mentor Graphics Corporation, Wilsonville, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corporation, Wilsonville, OR, USA","institution_ids":["https://openalex.org/I4210156212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075772311","display_name":"Kevin Hamilton","orcid":"https://orcid.org/0000-0002-3560-8097"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kevin Hamilton","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California, San Diego, La Jolla, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California, San Diego, La Jolla, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039615312","display_name":"Chung\u2010Kuan Cheng","orcid":"https://orcid.org/0000-0002-9865-8390"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chung-Kuan Cheng","raw_affiliation_strings":["Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6103,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.73965265,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"19","issue":"3","first_page":"520","last_page":"524"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7552424669265747},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.733348548412323},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.596174418926239},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.571167528629303},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5471287965774536},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4771125614643097},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.4476970434188843},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.42133674025535583},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4113911986351013},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.36096495389938354},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.30709922313690186},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.23714539408683777},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2187565565109253},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13055342435836792}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7552424669265747},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.733348548412323},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.596174418926239},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.571167528629303},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5471287965774536},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4771125614643097},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.4476970434188843},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.42133674025535583},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4113911986351013},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.36096495389938354},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.30709922313690186},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.23714539408683777},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2187565565109253},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13055342435836792},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2009.2035322","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2035322","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8899999856948853}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1645268237","https://openalex.org/W1996623312","https://openalex.org/W2012173826","https://openalex.org/W2042882340","https://openalex.org/W2087645421","https://openalex.org/W2102081731","https://openalex.org/W2117520286","https://openalex.org/W2130914360","https://openalex.org/W2146664966","https://openalex.org/W2154326380","https://openalex.org/W2157298832","https://openalex.org/W2158894965","https://openalex.org/W2162690634","https://openalex.org/W2167848093","https://openalex.org/W3147363670","https://openalex.org/W4231740337","https://openalex.org/W4236258190","https://openalex.org/W4255541183","https://openalex.org/W6679354847","https://openalex.org/W6681672822","https://openalex.org/W6817363484"],"related_works":["https://openalex.org/W2801840707","https://openalex.org/W2946034413","https://openalex.org/W2367009175","https://openalex.org/W1535238821","https://openalex.org/W2156891695","https://openalex.org/W1753758149","https://openalex.org/W1753381865","https://openalex.org/W2612178395","https://openalex.org/W1515275251","https://openalex.org/W2134904708"],"abstract_inverted_index":{"As":[0],"semiconductor":[1],"process":[2],"technology":[3],"scales":[4],"down,":[5],"interconnect":[6],"planning":[7],"presents":[8],"ever-greater":[9],"challenges":[10],"to":[11],"designers.":[12],"In":[13],"this":[14],"paper,":[15],"we":[16],"analyze,":[17],"evaluate,":[18],"and":[19,38,55],"compare":[20],"various":[21,48],"metrics":[22],"with":[23],"optimized":[24],"wire":[25],"configurations":[26],"in":[27],"the":[28,52],"contexts":[29],"of":[30,58],"different":[31],"design":[32,49],"criteria:":[33],"delay":[34,39],"minimization,":[35,37],"delay-power":[36],"<sup":[40],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[41],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[42],"-power":[43],"minimization.":[44],"We":[45],"show":[46],"how":[47],"criteria":[50],"influence":[51],"configuration,":[53],"performance,":[54],"power":[56],"consumption":[57],"repeated":[59],"wires.":[60]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
