{"id":"https://openalex.org/W2140331496","doi":"https://doi.org/10.1109/tvlsi.2009.2033356","title":"Design and Optimization of Power-Gated Circuits With Autonomous Data Retention","display_name":"Design and Optimization of Power-Gated Circuits With Autonomous Data Retention","publication_year":2009,"publication_date":"2009-11-23","ids":{"openalex":"https://openalex.org/W2140331496","doi":"https://doi.org/10.1109/tvlsi.2009.2033356","mag":"2140331496"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2009.2033356","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2033356","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039958474","display_name":"Jun Seomun","orcid":null},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jun Seomun","raw_affiliation_strings":["Department of Electrical Engineering, KAIST, Daejeon, South Korea","Dept. of Electr. Eng., KAIST\\\\, Daejeon, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, KAIST, Daejeon, South Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"Dept. of Electr. Eng., KAIST\\\\, Daejeon, South Korea","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020011072","display_name":"Youngsoo Shin","orcid":"https://orcid.org/0000-0002-7474-9212"},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Youngsoo Shin","raw_affiliation_strings":["Department of Electrical Engineering, KAIST, Daejeon, South Korea","Dept. of Electr. Eng., KAIST\\\\, Daejeon, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, KAIST, Daejeon, South Korea","institution_ids":["https://openalex.org/I157485424"]},{"raw_affiliation_string":"Dept. of Electr. Eng., KAIST\\\\, Daejeon, South Korea","institution_ids":["https://openalex.org/I157485424"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.2207,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.81763169,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"19","issue":"2","first_page":"227","last_page":"236"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.8638879060745239},{"id":"https://openalex.org/keywords/standby-power","display_name":"Standby power","score":0.8130217790603638},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.6788095235824585},{"id":"https://openalex.org/keywords/data-retention","display_name":"Data retention","score":0.6450668573379517},{"id":"https://openalex.org/keywords/subthreshold-conduction","display_name":"Subthreshold conduction","score":0.5525779128074646},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.5284751653671265},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.49728134274482727},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.48236721754074097},{"id":"https://openalex.org/keywords/power-optimization","display_name":"Power optimization","score":0.46154433488845825},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4536260664463043},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.44177955389022827},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4379338324069977},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.4166770577430725},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3894159197807312},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.24443206191062927},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1722712516784668}],"concepts":[{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.8638879060745239},{"id":"https://openalex.org/C7140552","wikidata":"https://www.wikidata.org/wiki/Q1366402","display_name":"Standby power","level":3,"score":0.8130217790603638},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.6788095235824585},{"id":"https://openalex.org/C2780866740","wikidata":"https://www.wikidata.org/wiki/Q5227345","display_name":"Data retention","level":2,"score":0.6450668573379517},{"id":"https://openalex.org/C156465305","wikidata":"https://www.wikidata.org/wiki/Q1658601","display_name":"Subthreshold conduction","level":4,"score":0.5525779128074646},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.5284751653671265},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.49728134274482727},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.48236721754074097},{"id":"https://openalex.org/C168292644","wikidata":"https://www.wikidata.org/wiki/Q10860336","display_name":"Power optimization","level":4,"score":0.46154433488845825},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4536260664463043},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.44177955389022827},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4379338324069977},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.4166770577430725},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3894159197807312},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.24443206191062927},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1722712516784668},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2009.2033356","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2033356","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W67633605","https://openalex.org/W1582019256","https://openalex.org/W1601651202","https://openalex.org/W2017370932","https://openalex.org/W2030607272","https://openalex.org/W2042151827","https://openalex.org/W2050462122","https://openalex.org/W2090940600","https://openalex.org/W2106157873","https://openalex.org/W2112690812","https://openalex.org/W2114621701","https://openalex.org/W2121225064","https://openalex.org/W2124276471","https://openalex.org/W2130968703","https://openalex.org/W2131862714","https://openalex.org/W2140210510","https://openalex.org/W2143727503","https://openalex.org/W2153506602","https://openalex.org/W2169033838","https://openalex.org/W2180646638","https://openalex.org/W2247347263","https://openalex.org/W4212765746","https://openalex.org/W4234463038","https://openalex.org/W4251099801","https://openalex.org/W6636174989"],"related_works":["https://openalex.org/W2075172982","https://openalex.org/W2012065800","https://openalex.org/W3013845316","https://openalex.org/W2124210802","https://openalex.org/W2783501501","https://openalex.org/W104239181","https://openalex.org/W3151319421","https://openalex.org/W2282162811","https://openalex.org/W2142785051","https://openalex.org/W3140192626"],"abstract_inverted_index":{"Power":[0],"gating":[1,92],"has":[2],"been":[3],"widely":[4],"employed":[5,167],"to":[6,19,67,110,124,152,168,172,185,210,218],"reduce":[7],"subthreshold":[8],"leakage.":[9],"Data":[10],"retention":[11,63,104,177],"elements":[12,35,76,105,178],"(flip-flops":[13],"and":[14,55,130,138,195,201,220,227,240],"isolation":[15],"circuits)":[16],"are":[17,29,134],"used":[18],"preserve":[20],"circuit":[21,59,115],"states":[22,28],"during":[23,234],"standby":[24,186,223],"mode,":[25],"if":[26],"the":[27,69,216,222,235],"needed":[30],"again":[31],"after":[32],"wake-up.":[33],"These":[34],"must":[36],"be":[37],"controlled":[38],"by":[39,82,136,162,225,238,250],"an":[40],"external":[41],"power":[42,91,126,212,245],"management":[43],"unit,":[44],"causing":[45],"a":[46,144,158,163],"network":[47],"of":[48,86,103,114,146],"control":[49,73,81,96,100],"signals":[50],"implemented":[51],"with":[52,60,118,203,230],"extra":[53],"wires":[54],"buffers.":[56],"A":[57],"power-gated":[58],"autonomous":[61],"data":[62],"(APG)":[64],"is":[65,108,166,199,247],"proposed":[66],"remove":[68],"overhead":[70],"involved":[71],"in":[72,77],"signals.":[74,101],"Retention":[75],"APG":[78,107,214],"derive":[79],"their":[80],"detecting":[83],"rising":[84],"potential":[85],"virtual":[87,155,173],"ground":[88,156],"rails":[89],"when":[90],"starts,":[93],"i.e.,":[94],"they":[95],"themselves":[97],"without":[98],"explicit":[99],"Design":[102],"for":[106,191],"addressed":[109],"facilitate":[111],"safe":[112],"capturing":[113],"states.":[116],"Experiments":[117,206],"65-nm":[119,204],"technology":[120],"demonstrate":[121],"that,":[122,208],"compared":[123,209],"standard":[125,211],"gating,":[127,213],"total":[128],"wirelength,":[129],"average":[131],"wiring":[132],"congestion":[133],"reduced":[135,249],"8.6%":[137],"4.1%":[139],"on":[140,252],"average,":[141],"respectively,":[142,229],"at":[143],"cost":[145],"6.8%":[147],"area":[148],"increase.":[149],"In":[150],"order":[151],"fast":[153],"charge":[154],"rails,":[157],"pMOS":[159,193],"switch":[160,194],"driven":[161],"short":[164],"pulse":[165,197],"directly":[169],"provide":[170],"charges":[171],"ground.":[174],"This":[175],"helps":[176],"avoid":[179],"short-circuit":[180],"current":[181],"while":[182],"making":[183],"transition":[184],"mode.":[187],"The":[188],"optimization":[189],"procedure":[190],"sizing":[192],"deciding":[196],"width":[198],"addressed,":[200],"assessed":[202],"technology.":[205],"show":[207],"reduces":[215],"delay":[217],"enter":[219],"exit":[221],"mode":[224,243],"65.6%":[226],"28.9%,":[228],"corresponding":[231],"energy":[232],"dissipation":[233],"period":[236],"cut":[237],"46.1%":[239],"36.5%.":[241],"Standby":[242],"leakage":[244],"consumption":[246],"also":[248],"15.8%":[251],"average.":[253]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2014,"cited_by_count":3},{"year":2012,"cited_by_count":3}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
