{"id":"https://openalex.org/W2149996407","doi":"https://doi.org/10.1109/tvlsi.2009.2030156","title":"An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement","display_name":"An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement","publication_year":2009,"publication_date":"2009-10-13","ids":{"openalex":"https://openalex.org/W2149996407","doi":"https://doi.org/10.1109/tvlsi.2009.2030156","mag":"2149996407"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2009.2030156","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2030156","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030467159","display_name":"Weixiang Shen","orcid":"https://orcid.org/0000-0002-4666-5126"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Weixiang Shen","raw_affiliation_strings":["EDA Laboratory Department of Computer Science and Technology, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"EDA Laboratory Department of Computer Science and Technology, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100894724","display_name":"Yici Cai","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yici Cai","raw_affiliation_strings":["EDA Laboratory Department of Computer Science and Technology, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"EDA Laboratory Department of Computer Science and Technology, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111768666","display_name":"Xianlong Hong","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xianlong Hong","raw_affiliation_strings":["EDA Laboratory Department of Computer Science and Technology, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"EDA Laboratory Department of Computer Science and Technology, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103246390","display_name":"Jiang Hu","orcid":"https://orcid.org/0000-0003-1157-7799"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jiang Hu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Texas A and M University, College Station, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Texas A and M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5030467159"],"corresponding_institution_ids":["https://openalex.org/I99065089"],"apc_list":null,"apc_paid":null,"fwci":2.3744,"has_fulltext":false,"cited_by_count":40,"citation_normalized_percentile":{"value":0.89570794,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"18","issue":"12","first_page":"1639","last_page":"1648"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.921306848526001},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.6978058218955994},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6826885938644409},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.6288602352142334},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.6259350776672363},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.5864835381507874},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5839765071868896},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.494578093290329},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.49401289224624634},{"id":"https://openalex.org/keywords/vector-clock","display_name":"Vector clock","score":0.4654444456100464},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3814261257648468},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38141465187072754},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.34954574704170227},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.3086872100830078},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.2657773494720459},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08188262581825256}],"concepts":[{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.921306848526001},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.6978058218955994},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6826885938644409},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.6288602352142334},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.6259350776672363},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.5864835381507874},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5839765071868896},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.494578093290329},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.49401289224624634},{"id":"https://openalex.org/C52563298","wikidata":"https://www.wikidata.org/wiki/Q1413349","display_name":"Vector clock","level":5,"score":0.4654444456100464},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3814261257648468},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38141465187072754},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34954574704170227},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.3086872100830078},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.2657773494720459},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08188262581825256},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2009.2030156","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2030156","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1819510856","https://openalex.org/W1970310355","https://openalex.org/W2095310213","https://openalex.org/W2096050740","https://openalex.org/W2113775750","https://openalex.org/W2127406844","https://openalex.org/W2128876681","https://openalex.org/W2129107674","https://openalex.org/W2136047350","https://openalex.org/W2136768070","https://openalex.org/W2142838686","https://openalex.org/W2143629014","https://openalex.org/W2150499679","https://openalex.org/W2163899785","https://openalex.org/W2172010755","https://openalex.org/W4249004757","https://openalex.org/W6679411101"],"related_works":["https://openalex.org/W2040807843","https://openalex.org/W4249038728","https://openalex.org/W4231008241","https://openalex.org/W2125201667","https://openalex.org/W2163637408","https://openalex.org/W2617666058","https://openalex.org/W2787237207","https://openalex.org/W1999924508","https://openalex.org/W2520965597","https://openalex.org/W1938797020"],"abstract_inverted_index":{"Clock":[0,39],"gating":[1,40,66,146],"is":[2,44,67,77,154],"one":[3],"of":[4,22,84],"the":[5,23,52,74,82,89,130,139,149,152],"most":[6,21],"effective":[7],"techniques":[8],"to":[9,28,51,81,151],"reduce":[10],"clock":[11,35,65,71,104,116,122,134,140],"tree":[12,36,72,105,117,123,141],"power.":[13],"Although":[14],"it":[15,47,56],"has":[16],"already":[17],"been":[18],"studied":[19],"considerably,":[20],"previous":[24,131],"works":[25,132],"are":[26],"restricted":[27],"either":[29],"register":[30,119],"transfer":[31],"level":[32],"(RTL)":[33],"or":[34],"synthesis":[37],"stage.":[38],"design":[41,106],"at":[42,70],"RTL":[43],"coarse":[45],"and":[46,91,125],"pays":[48],"no":[49],"attention":[50],"physical":[53,92],"information,":[54],"therefore,":[55,148],"often":[57],"results":[58],"in":[59,107],"large":[60],"wirelength":[61],"overhead.":[62],"While":[63],"if":[64],"considered":[68],"only":[69],"synthesis,":[73],"optimization":[75],"space":[76],"largely":[78],"limited":[79],"due":[80],"fixing":[83],"registers.":[85],"To":[86],"fully":[87],"use":[88],"logical":[90],"information":[93],"between":[94],"registers,":[95],"we":[96],"propose":[97],"a":[98],"new":[99],"flow":[100],"for":[101],"low-power":[102],"gated":[103,115,121],"this":[108],"work.":[109],"It":[110],"mainly":[111],"includes":[112],"three":[113],"parts:":[114],"aware":[118],"placement,":[120],"construction,":[124],"incremental":[126],"placement.":[127],"Compared":[128],"with":[129,143],"on":[133],"gating,":[135],"our":[136],"algorithm":[137],"reduces":[138],"power":[142],"much":[144],"fewer":[145],"logics,":[147],"overhead":[150],"placement":[153],"also":[155],"reduced.":[156]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":4},{"year":2012,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}