{"id":"https://openalex.org/W2087748293","doi":"https://doi.org/10.1109/tvlsi.2009.2029276","title":"Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating","display_name":"Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating","publication_year":2009,"publication_date":"2009-10-16","ids":{"openalex":"https://openalex.org/W2087748293","doi":"https://doi.org/10.1109/tvlsi.2009.2029276","mag":"2087748293"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2009.2029276","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2029276","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006552035","display_name":"Ashoka Sathanur","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Ashoka Sathanur","raw_affiliation_strings":["Dipartimento di Automatica e Informatica (DAUIN), Politecnico di Turino, Torino, Italy","Dipt. di Autom. e Inf. (DAUIN), Politec. di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica (DAUIN), Politecnico di Turino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dipt. di Autom. e Inf. (DAUIN), Politec. di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I4210148700","display_name":"Istituto Nazionale di Fisica Nucleare, Sezione di Bologna","ror":"https://ror.org/04j0x0h93","country_code":"IT","type":"facility","lineage":["https://openalex.org/I160013858","https://openalex.org/I4210148700"]},{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["Dipartimento di Elettronica, Informatica e Sistemistica (DEIS), Universit\u00e0 di Bologna, Bologna, Italy","Dipt. di Elettron., Inf. e Sist. (DEIS), Univ. di Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Informatica e Sistemistica (DEIS), Universit\u00e0 di Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"Dipt. di Elettron., Inf. e Sist. (DEIS), Univ. di Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I4210148700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058379509","display_name":"Alberto Macii","orcid":"https://orcid.org/0000-0002-8869-5710"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Alberto Macii","raw_affiliation_strings":["Dipartimento di Automatica e Informatica (DAUIN), Politecnico di Turino, Torino, Italy","Dipt. di Autom. e Inf. (DAUIN), Politec. di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica (DAUIN), Politecnico di Turino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dipt. di Autom. e Inf. (DAUIN), Politec. di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005432629","display_name":"Enrico Macii","orcid":"https://orcid.org/0000-0001-9046-5618"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Enrico Macii","raw_affiliation_strings":["Dipartimento di Automatica e Informatica (DAUIN), Politecnico di Turino, Torino, Italy","Dipt. di Autom. e Inf. (DAUIN), Politec. di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica (DAUIN), Politecnico di Turino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dipt. di Autom. e Inf. (DAUIN), Politec. di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024891882","display_name":"Massimo Poncino","orcid":"https://orcid.org/0000-0002-1369-9688"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Massimo Poncino","raw_affiliation_strings":["Dipartimento di Automatica e Informatica (DAUIN), Politecnico di Turino, Torino, Italy","Dipt. di Autom. e Inf. (DAUIN), Politec. di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica (DAUIN), Politecnico di Turino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dipt. di Autom. e Inf. (DAUIN), Politec. di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5006552035"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":0.6096,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.72019008,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"19","issue":"1","first_page":"146","last_page":"151"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.8311617970466614},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.6983533501625061},{"id":"https://openalex.org/keywords/upper-and-lower-bounds","display_name":"Upper and lower bounds","score":0.5989393591880798},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5956494212150574},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5918828845024109},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4650745391845703},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4488360285758972},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.4165083169937134},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.41315895318984985},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.35463276505470276},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2992475628852844},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23557692766189575},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1982002556324005},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10423943400382996}],"concepts":[{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.8311617970466614},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.6983533501625061},{"id":"https://openalex.org/C77553402","wikidata":"https://www.wikidata.org/wiki/Q13222579","display_name":"Upper and lower bounds","level":2,"score":0.5989393591880798},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5956494212150574},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5918828845024109},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4650745391845703},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4488360285758972},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.4165083169937134},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.41315895318984985},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.35463276505470276},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2992475628852844},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23557692766189575},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1982002556324005},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10423943400382996},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tvlsi.2009.2029276","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2029276","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:cris.unibo.it:11585/105832","is_oa":false,"landing_page_url":"http://hdl.handle.net/11585/105832","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:porto.polito.it:2374921","is_oa":false,"landing_page_url":"http://porto.polito.it/2374921/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISSN:1063-8210","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1582019256","https://openalex.org/W2023765806","https://openalex.org/W2076469371","https://openalex.org/W2086839192","https://openalex.org/W2096424065","https://openalex.org/W2105743938","https://openalex.org/W2109797003","https://openalex.org/W2126693329","https://openalex.org/W2131862714","https://openalex.org/W2135159456","https://openalex.org/W2136446383","https://openalex.org/W2137707668","https://openalex.org/W2138858358","https://openalex.org/W2140000007","https://openalex.org/W2145525199","https://openalex.org/W2152406824","https://openalex.org/W2173072002","https://openalex.org/W3140053820","https://openalex.org/W6656120514","https://openalex.org/W6678797189"],"related_works":["https://openalex.org/W2375463041","https://openalex.org/W2113774150","https://openalex.org/W1501225614","https://openalex.org/W1583123542","https://openalex.org/W2184099353","https://openalex.org/W2164242767","https://openalex.org/W2113758237","https://openalex.org/W2166369057","https://openalex.org/W2789295024","https://openalex.org/W2140480554"],"abstract_inverted_index":{"The":[0,123,145],"capability":[1],"of":[2,8,28,83,158],"accurately":[3],"estimating":[4],"an":[5,89,137],"upper":[6,60,113],"bound":[7,114],"the":[9,18,34,43,78,84,154],"maximum":[10,35,85],"current":[11,36,87,101],"drawn":[12,86],"by":[13],"a":[14,25,48,66,108,117],"digital":[15],"macroblock":[16],"from":[17],"ground":[19],"or":[20],"power":[21,143],"supply":[22],"line":[23],"constitutes":[24],"major":[26],"asset":[27],"automatic":[29],"power-gating":[30,139],"flows.":[31],"In":[32,103],"fact,":[33],"information":[37],"is":[38,88,133],"essential":[39],"to":[40,73],"properly":[41],"size":[42],"sleep":[44,75],"transistor":[45],"in":[46],"such":[47],"way":[49],"that":[50],"speed":[51],"degradation":[52],"and":[53,119,131,156],"signal":[54],"integrity":[55],"violations":[56],"are":[57,97],"avoided.":[58],"Loose":[59],"bounds":[61],"can":[62],"be":[63],"determined":[64],"with":[65,116],"reasonable":[67],"computational":[68,121],"cost,":[69],"but":[70],"they":[71],"lead":[72],"oversized":[74],"transistors.":[76],"On":[77],"other":[79],"hand,":[80],"exact":[81],"computation":[82],"NP-hard":[90],"problem,":[91],"even":[92],"when":[93],"conservative":[94],"simplifying":[95],"assumptions":[96],"made":[98],"on":[99,150],"gate-level":[100],"profiles.":[102],"this":[104],"paper,":[105],"we":[106,147],"present":[107],"scalable":[109],"algorithm":[110,124],"for":[111,141],"tightening":[112],"computation,":[115],"controlled":[118],"tunable":[120],"cost.":[122],"exploits":[125],"state-of-the-art":[126],"commercial":[127],"timing":[128],"analysis":[129],"engines,":[130],"it":[132],"tightly":[134],"integrated":[135],"into":[136],"industrial":[138],"flow":[140],"leakage":[142],"reduction.":[144],"results":[146],"have":[148],"obtained":[149],"large":[151],"circuits":[152],"demonstrate":[153],"scalability":[155],"effectiveness":[157],"our":[159],"estimation":[160],"approach.":[161]},"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}