{"id":"https://openalex.org/W2119982490","doi":"https://doi.org/10.1109/tvlsi.2009.2025279","title":"Process-Variation Resilient and Voltage-Scalable DCT Architecture for Robust Low-Power Computing","display_name":"Process-Variation Resilient and Voltage-Scalable DCT Architecture for Robust Low-Power Computing","publication_year":2009,"publication_date":"2009-11-17","ids":{"openalex":"https://openalex.org/W2119982490","doi":"https://doi.org/10.1109/tvlsi.2009.2025279","mag":"2119982490"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2009.2025279","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2025279","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077501734","display_name":"Georgios Karakonstantis","orcid":"https://orcid.org/0000-0002-5693-8503"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Georgios Karakonstantis","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012819177","display_name":"Nilanjan Banerjee","orcid":"https://orcid.org/0000-0003-4466-0898"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nilanjan Banerjee","raw_affiliation_strings":["Microprocessor Research Laboratory, Intel Corporation, Santa Clara, CA, USA","School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Research Laboratory, Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031161187","display_name":"Kaushik Roy","orcid":"https://orcid.org/0000-0002-0735-9695"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kaushik Roy","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.923,"has_fulltext":false,"cited_by_count":41,"citation_normalized_percentile":{"value":0.90557314,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"18","issue":"10","first_page":"1461","last_page":"1470"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/discrete-cosine-transform","display_name":"Discrete cosine transform","score":0.7217954397201538},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.6600172519683838},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.6196650266647339},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5777177810668945},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5633885264396667},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5227668285369873},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.5200448036193848},{"id":"https://openalex.org/keywords/dynamic-voltage-scaling","display_name":"Dynamic voltage scaling","score":0.4759138226509094},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.4701654613018036},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4558819532394409},{"id":"https://openalex.org/keywords/low-voltage","display_name":"Low voltage","score":0.4532145857810974},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4364303946495056},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.39193448424339294},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21893492341041565},{"id":"https://openalex.org/keywords/image","display_name":"Image (mathematics)","score":0.18192893266677856},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.17504161596298218},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1603676974773407},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.11347025632858276},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.09771573543548584}],"concepts":[{"id":"https://openalex.org/C2221639","wikidata":"https://www.wikidata.org/wiki/Q2877","display_name":"Discrete cosine transform","level":3,"score":0.7217954397201538},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.6600172519683838},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.6196650266647339},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5777177810668945},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5633885264396667},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5227668285369873},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.5200448036193848},{"id":"https://openalex.org/C2776047111","wikidata":"https://www.wikidata.org/wiki/Q632037","display_name":"Dynamic voltage scaling","level":3,"score":0.4759138226509094},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.4701654613018036},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4558819532394409},{"id":"https://openalex.org/C128624480","wikidata":"https://www.wikidata.org/wiki/Q1504817","display_name":"Low voltage","level":3,"score":0.4532145857810974},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4364303946495056},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.39193448424339294},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21893492341041565},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.18192893266677856},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.17504161596298218},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1603676974773407},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.11347025632858276},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.09771573543548584},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tvlsi.2009.2025279","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2025279","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.454.952","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.454.952","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://web.ics.purdue.edu/~gkarakon/TVLSI_.PDF","raw_type":"text"},{"id":"pmh:oai:pure.qub.ac.uk/portal:publications/6cd7c7a1-34df-4b08-9d82-db12059fb629","is_oa":false,"landing_page_url":"https://pure.qub.ac.uk/en/publications/6cd7c7a1-34df-4b08-9d82-db12059fb629","pdf_url":null,"source":{"id":"https://openalex.org/S4306402319","display_name":"Research Portal (Queen's University Belfast)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I126231945","host_organization_name":"Queen's University Belfast","host_organization_lineage":["https://openalex.org/I126231945"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Karakonstantis , G , Banerjee , N & Roy , K 2010 , ' Process-variation resilient and voltage-scalable dct architecture for robust low-power computing ' , IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol. 18 , no. 10 , pp. 1461-1470 . https://doi.org/10.1109/TVLSI.2009.2025279","raw_type":"article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7300000190734863,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W1521141427","https://openalex.org/W1541389308","https://openalex.org/W1543643719","https://openalex.org/W1544057354","https://openalex.org/W1647445161","https://openalex.org/W1668551150","https://openalex.org/W1963746503","https://openalex.org/W2081396243","https://openalex.org/W2099679924","https://openalex.org/W2104677471","https://openalex.org/W2105390617","https://openalex.org/W2108049334","https://openalex.org/W2115722171","https://openalex.org/W2116758369","https://openalex.org/W2117648153","https://openalex.org/W2123021960","https://openalex.org/W2131581217","https://openalex.org/W2136784715","https://openalex.org/W2149009819","https://openalex.org/W2158664566","https://openalex.org/W2172699263","https://openalex.org/W3023411394","https://openalex.org/W3139678091","https://openalex.org/W3149416473","https://openalex.org/W4236432903","https://openalex.org/W4240374004","https://openalex.org/W6637003604","https://openalex.org/W6675905758","https://openalex.org/W6677360253"],"related_works":["https://openalex.org/W1916685473","https://openalex.org/W2055682261","https://openalex.org/W2186390138","https://openalex.org/W1993363272","https://openalex.org/W2060035984","https://openalex.org/W2790129917","https://openalex.org/W2594429115","https://openalex.org/W2053154428","https://openalex.org/W2155832338","https://openalex.org/W2139512173"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"present":[4],"a":[5,34,67,114,119,145],"novel":[6],"discrete":[7],"cosine":[8],"transform":[9],"(DCT)":[10],"architecture":[11,65],"that":[12,53,87],"allows":[13,66],"aggressive":[14,76,99],"voltage":[15,37,77,101,109],"scaling":[16,78,102],"for":[17,113,135],"low-power":[18],"dissipation,":[19],"even":[20,88],"under":[21,75,89],"process":[22,41,83,91,147],"parameter":[23],"variations":[24,39,92],"with":[25,125],"minimal":[26],"overhead":[27],"as":[28,79,81],"opposed":[29],"to":[30,56,60,141],"existing":[31,142],"techniques.":[32],"Under":[33],"scaled":[35],"supply":[36,100],"and/or":[38],"in":[40,70,144],"parameters,":[42],"any":[43],"possible":[44],"delay":[45],"errors":[46],"appear":[47],"only":[48],"from":[49],"the":[50,71,107,136],"long":[51],"paths":[52],"are":[54],"designed":[55],"be":[57],"less":[58],"contributive":[59],"output":[61],"quality.":[62],"The":[63],"proposed":[64,137],"graceful":[68],"degradation":[69,121],"peak":[72],"SNR":[73],"(PSNR)":[74],"well":[80],"extreme":[82],"variations.":[84],"Results":[85],"show":[86],"large":[90],"(\u00b13\u03c3":[93],"around":[94],"mean":[95],"threshold":[96],"voltage)":[97],"and":[98],"(at":[103],"0.88":[104],"V,":[105],"while":[106],"nominal":[108],"is":[110,118],"1.2":[111],"V":[112],"90-nm":[115,146],"technology),":[116],"there":[117],"gradual":[120],"of":[122,132],"image":[123],"quality":[124],"considerable":[126],"power":[127],"savings":[128],"(71%":[129],"at":[130],"PSNR":[131],"23.4":[133],"dB)":[134],"architecture,":[138],"when":[139],"compared":[140],"implementations":[143],"technology.":[148]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}