{"id":"https://openalex.org/W2112870827","doi":"https://doi.org/10.1109/tvlsi.2009.2022531","title":"Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking","display_name":"Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking","publication_year":2009,"publication_date":"2009-11-03","ids":{"openalex":"https://openalex.org/W2112870827","doi":"https://doi.org/10.1109/tvlsi.2009.2022531","mag":"2112870827"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2009.2022531","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2022531","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085567454","display_name":"Swaroop Ghosh","orcid":"https://orcid.org/0000-0001-8753-490X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Swaroop Ghosh","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","Logic Technol. Dev., Adv. Memory Design Group, Intel Inc., Portland, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Logic Technol. Dev., Adv. Memory Design Group, Intel Inc., Portland, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5106083836","display_name":"Debabrata Mohapatra","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Debabrata Mohapatra","raw_affiliation_strings":["Logic Technology Development, Advanced Memory Design, Intel, Inc., Portland, OR, USA","Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Logic Technology Development, Advanced Memory Design, Intel, Inc., Portland, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077501734","display_name":"Georgios Karakonstantis","orcid":"https://orcid.org/0000-0002-5693-8503"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Georgios Karakonstantis","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046257293","display_name":"Kaushik Roy","orcid":"https://orcid.org/0000-0003-4937-2115"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kaushik Roy","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.4022,"has_fulltext":false,"cited_by_count":60,"citation_normalized_percentile":{"value":0.89172075,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"18","issue":"9","first_page":"1301","last_page":"1309"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.9150450229644775},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8351346850395203},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6042755246162415},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5893964767456055},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.5308018326759338},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4722713232040405},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.46864670515060425},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4480679929256439},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.41084447503089905},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.33478865027427673},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.33193239569664},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.32994896173477173},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.24379411339759827},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.23148849606513977},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.189067542552948},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13087624311447144}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.9150450229644775},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8351346850395203},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6042755246162415},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5893964767456055},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.5308018326759338},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4722713232040405},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.46864670515060425},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4480679929256439},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.41084447503089905},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.33478865027427673},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33193239569664},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.32994896173477173},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.24379411339759827},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.23148849606513977},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.189067542552948},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13087624311447144},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tvlsi.2009.2022531","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2022531","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:pure.qub.ac.uk/portal:publications/27482c07-2683-473d-a7e7-a8612da32b76","is_oa":false,"landing_page_url":"http://www.scopus.com/inward/record.url?eid=2-s2.0-77956230601&partnerID=8YFLogxK","pdf_url":null,"source":{"id":"https://openalex.org/S4306402319","display_name":"Research Portal (Queen's University Belfast)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I126231945","host_organization_name":"Queen's University Belfast","host_organization_lineage":["https://openalex.org/I126231945"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Ghosh , S , Mohapatra , D , Karakonstantis , G &amp; Roy , K 2010 , ' Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking ' , IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol. 18 , no. 9 , pp. 1301-1309 . https://doi.org/10.1109/TVLSI.2009.2022531","raw_type":"article"},{"id":"pmh:oai:pure.qub.ac.uk/portal:publications/27482c07-2683-473d-a7e7-a8612da32b76","is_oa":false,"landing_page_url":"https://pure.qub.ac.uk/en/publications/27482c07-2683-473d-a7e7-a8612da32b76","pdf_url":null,"source":{"id":"https://openalex.org/S4306402319","display_name":"Research Portal (Queen's University Belfast)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I126231945","host_organization_name":"Queen's University Belfast","host_organization_lineage":["https://openalex.org/I126231945"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Ghosh, S, Mohapatra, D, Karakonstantis, G & Roy, K 2010, 'Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking', IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 9, pp. 1301-1309. https://doi.org/10.1109/TVLSI.2009.2022531","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6899999976158142,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1963965124","https://openalex.org/W2038840127","https://openalex.org/W2053325738","https://openalex.org/W2108890336","https://openalex.org/W2109234924","https://openalex.org/W2115686854","https://openalex.org/W2147847555","https://openalex.org/W2156359452","https://openalex.org/W2157024459","https://openalex.org/W2162250277","https://openalex.org/W2168543008","https://openalex.org/W3103339143","https://openalex.org/W6676816201"],"related_works":["https://openalex.org/W2183015194","https://openalex.org/W2113599973","https://openalex.org/W2059812140","https://openalex.org/W2070693700","https://openalex.org/W4233226037","https://openalex.org/W1975649745","https://openalex.org/W2610514210","https://openalex.org/W90892980","https://openalex.org/W1548741926","https://openalex.org/W2113434540"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"explore":[4],"various":[5],"arithmetic":[6,33,58],"units":[7,34,50,97],"for":[8],"possible":[9],"use":[10],"in":[11,72,80,90],"high-speed,":[12],"high-yield":[13],"ALUs":[14,106],"operated":[15],"at":[16,92,110],"scaled":[17],"supply":[18,45],"voltage":[19,46,103],"with":[20,86,114],"adaptive":[21],"clock":[22,112,121],"stretching.":[23,122],"We":[24],"demonstrate":[25],"that":[26,107],"careful":[27],"logic":[28],"optimization":[29],"of":[30,56],"the":[31,60],"existing":[32],"(to":[35],"create":[36],"hybrid":[37,49],"units)":[38],"indeed":[39],"make":[40],"them":[41],"further":[42],"amenable":[43],"to":[44,83,101,119],"scaling.":[47],"Such":[48],"result":[51],"from":[52],"mixing":[53],"right":[54],"amount":[55],"fast":[57],"into":[59],"slower":[61],"ones.":[62],"Simulations":[63],"on":[64],"different":[65],"<i":[66],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[67],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">hybrid</i>":[68],"adder":[69],"and":[70],"multipliers":[71],"BPTM":[73],"70":[74],"nm":[75],"technology":[76],"show":[77],"18%-50%":[78],"improvements":[79],"power":[81],"compared":[82],"standard":[84],"adders":[85],"only":[87],"2%-8%":[88],"increase":[89],"die-area":[91],"iso-yield.":[93],"These":[94],"optimized":[95],"datapath":[96],"can":[98,108],"be":[99],"used":[100],"construct":[102],"scalable":[104],"robust":[105],"operate":[109],"high":[111],"frequency":[113],"minimal":[115],"performance":[116],"degradation":[117],"due":[118],"occasional":[120]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":8},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
