{"id":"https://openalex.org/W2159217072","doi":"https://doi.org/10.1109/tvlsi.2009.2017750","title":"A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration","display_name":"A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration","publication_year":2009,"publication_date":"2009-08-25","ids":{"openalex":"https://openalex.org/W2159217072","doi":"https://doi.org/10.1109/tvlsi.2009.2017750","mag":"2159217072"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2009.2017750","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2017750","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048717783","display_name":"Aamir Zia","orcid":null},"institutions":[{"id":"https://openalex.org/I165799507","display_name":"Rensselaer Polytechnic Institute","ror":"https://ror.org/01rtyzb94","country_code":"US","type":"education","lineage":["https://openalex.org/I165799507"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Aamir Zia","raw_affiliation_strings":["Electrical, Computer and Systems Engineering Department and the Center of Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY, USA"],"affiliations":[{"raw_affiliation_string":"Electrical, Computer and Systems Engineering Department and the Center of Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103342202","display_name":"Philip Jacob","orcid":null},"institutions":[{"id":"https://openalex.org/I165799507","display_name":"Rensselaer Polytechnic Institute","ror":"https://ror.org/01rtyzb94","country_code":"US","type":"education","lineage":["https://openalex.org/I165799507"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Philip Jacob","raw_affiliation_strings":["Electrical, Computer and Systems Engineering Department and the Center of Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY, USA"],"affiliations":[{"raw_affiliation_string":"Electrical, Computer and Systems Engineering Department and the Center of Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100434618","display_name":"Jinwoo Kim","orcid":"https://orcid.org/0000-0003-4380-6656"},"institutions":[{"id":"https://openalex.org/I165799507","display_name":"Rensselaer Polytechnic Institute","ror":"https://ror.org/01rtyzb94","country_code":"US","type":"education","lineage":["https://openalex.org/I165799507"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jin-Woo Kim","raw_affiliation_strings":["Electrical, Computer and Systems Engineering Department and the Center of Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY, USA"],"affiliations":[{"raw_affiliation_string":"Electrical, Computer and Systems Engineering Department and the Center of Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109897442","display_name":"Michael Chu","orcid":null},"institutions":[{"id":"https://openalex.org/I165799507","display_name":"Rensselaer Polytechnic Institute","ror":"https://ror.org/01rtyzb94","country_code":"US","type":"education","lineage":["https://openalex.org/I165799507"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael Chu","raw_affiliation_strings":["Electrical, Computer and Systems Engineering Department and the Center of Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY, USA"],"affiliations":[{"raw_affiliation_string":"Electrical, Computer and Systems Engineering Department and the Center of Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113702863","display_name":"Russell P. Kraft","orcid":null},"institutions":[{"id":"https://openalex.org/I165799507","display_name":"Rensselaer Polytechnic Institute","ror":"https://ror.org/01rtyzb94","country_code":"US","type":"education","lineage":["https://openalex.org/I165799507"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Russell P. Kraft","raw_affiliation_strings":["Electrical, Computer and Systems Engineering Department and the Center of Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY, USA"],"affiliations":[{"raw_affiliation_string":"Electrical, Computer and Systems Engineering Department and the Center of Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038903084","display_name":"J. F. McDonald","orcid":"https://orcid.org/0000-0003-1058-6845"},"institutions":[{"id":"https://openalex.org/I165799507","display_name":"Rensselaer Polytechnic Institute","ror":"https://ror.org/01rtyzb94","country_code":"US","type":"education","lineage":["https://openalex.org/I165799507"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John F. McDonald","raw_affiliation_strings":["Electrical, Computer and Systems Engineering Department and the Center of Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY, USA"],"affiliations":[{"raw_affiliation_string":"Electrical, Computer and Systems Engineering Department and the Center of Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY, USA","institution_ids":["https://openalex.org/I165799507"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5048717783"],"corresponding_institution_ids":["https://openalex.org/I165799507"],"apc_list":null,"apc_paid":null,"fwci":2.3926,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.89450902,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"18","issue":"6","first_page":"967","last_page":"977"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7294032573699951},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6335543990135193},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.5940909385681152},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5110763311386108},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.47937944531440735},{"id":"https://openalex.org/keywords/pipeline-burst-cache","display_name":"Pipeline burst cache","score":0.4741986393928528},{"id":"https://openalex.org/keywords/page-cache","display_name":"Page cache","score":0.4736579358577728},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.4510839879512787},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.440751314163208},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41297537088394165},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38285303115844727},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.34707513451576233}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7294032573699951},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6335543990135193},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.5940909385681152},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5110763311386108},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.47937944531440735},{"id":"https://openalex.org/C157547923","wikidata":"https://www.wikidata.org/wiki/Q7197276","display_name":"Pipeline burst cache","level":5,"score":0.4741986393928528},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.4736579358577728},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.4510839879512787},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.440751314163208},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41297537088394165},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38285303115844727},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.34707513451576233}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2009.2017750","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2017750","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.800000011920929,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320310013","display_name":"North Carolina State University","ror":"https://ror.org/04tj63d06"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1588110940","https://openalex.org/W2005226599","https://openalex.org/W2100913437","https://openalex.org/W2110444864","https://openalex.org/W2114498658","https://openalex.org/W2120238222","https://openalex.org/W2128485160","https://openalex.org/W2129125546","https://openalex.org/W2132942644","https://openalex.org/W2137893918","https://openalex.org/W2141363922","https://openalex.org/W2141736089","https://openalex.org/W2145135695","https://openalex.org/W2145547293","https://openalex.org/W2152121447","https://openalex.org/W2154826082","https://openalex.org/W2168514350","https://openalex.org/W6681089294"],"related_works":["https://openalex.org/W2399041033","https://openalex.org/W2072955902","https://openalex.org/W2081928868","https://openalex.org/W2141363922","https://openalex.org/W2000122388","https://openalex.org/W2088347047","https://openalex.org/W2162744059","https://openalex.org/W3140186264","https://openalex.org/W12620440","https://openalex.org/W2944770876"],"abstract_inverted_index":{"Slow":[0],"cache":[1,51,81,97],"memory":[2,6,22],"systems":[3],"and":[4,21,39,61,102],"low":[5,40],"bandwidth":[7,38,109],"present":[8],"a":[9,25,29,36,47,53,64],"major":[10],"bottleneck":[11],"in":[12,63],"performance":[13],"of":[14,19],"modern":[15],"microprocessors.":[16],"3-D":[17,49,54,80],"integration":[18],"processor":[20],"subsystems":[23],"provides":[24],"means":[26],"to":[27,105],"realize":[28],"wide":[30,74],"data":[31,75],"bus":[32,76],"that":[33],"could":[34],"provide":[35],"high":[37],"latency":[41],"on-chip":[42],"cache.":[43],"This":[44],"paper":[45],"presents":[46],"three-tier,":[48],"192-kB":[50],"for":[52,77],"processor-memory":[55],"stack.":[56],"The":[57,95],"chip":[58],"is":[59,85],"designed":[60],"fabricated":[62,96],"0.18":[65],"m":[66],"fully":[67],"depleted":[68],"SOI":[69],"CMOS":[70],"process.":[71],"An":[72],"ultra":[73],"connecting":[78],"the":[79,83,92,111],"with":[82],"microprocessor":[84],"implemented":[86],"using":[87],"dense":[88],"vertical":[89],"vias":[90],"between":[91],"stacked":[93],"wafers.":[94],"operates":[98],"at":[99,110],"500":[100],"MHz":[101],"achieves":[103],"up":[104],"96":[106],"GB/s":[107],"aggregate":[108],"output.":[112]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}