{"id":"https://openalex.org/W2116194281","doi":"https://doi.org/10.1109/tvlsi.2009.2017122","title":"A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC","display_name":"A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC","publication_year":2009,"publication_date":"2009-07-01","ids":{"openalex":"https://openalex.org/W2116194281","doi":"https://doi.org/10.1109/tvlsi.2009.2017122","mag":"2116194281"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2009.2017122","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2017122","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044791537","display_name":"Chao-Yang Kao","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Chao-Yang Kao","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]},{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan#TAB#","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071624937","display_name":"Youn-Long Lin","orcid":"https://orcid.org/0000-0002-4106-8082"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Youn-Long Lin","raw_affiliation_strings":["Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]},{"raw_affiliation_string":"Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan#TAB#","institution_ids":["https://openalex.org/I25846049"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5044791537"],"corresponding_institution_ids":["https://openalex.org/I25846049"],"apc_list":null,"apc_paid":null,"fwci":3.8771,"has_fulltext":false,"cited_by_count":30,"citation_normalized_percentile":{"value":0.93640915,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"18","issue":"6","first_page":"866","last_page":"874"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10531","display_name":"Advanced Vision and Imaging","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11165","display_name":"Image and Video Quality Assessment","score":0.9940000176429749,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7640727758407593},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6665452718734741},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6018246412277222},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5720066428184509},{"id":"https://openalex.org/keywords/motion-estimation","display_name":"Motion estimation","score":0.5477896332740784},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5456098914146423},{"id":"https://openalex.org/keywords/block-size","display_name":"Block size","score":0.5120423436164856},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.49401599168777466},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.4791407287120819},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4641808867454529},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4245935082435608},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.36873018741607666},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2795991003513336},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2603176236152649},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.1823744773864746},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.13753756880760193},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10584887862205505},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10346898436546326}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7640727758407593},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6665452718734741},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6018246412277222},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5720066428184509},{"id":"https://openalex.org/C10161872","wikidata":"https://www.wikidata.org/wiki/Q557891","display_name":"Motion estimation","level":2,"score":0.5477896332740784},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5456098914146423},{"id":"https://openalex.org/C41431624","wikidata":"https://www.wikidata.org/wiki/Q1053357","display_name":"Block size","level":3,"score":0.5120423436164856},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.49401599168777466},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.4791407287120819},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4641808867454529},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4245935082435608},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.36873018741607666},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2795991003513336},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2603176236152649},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.1823744773864746},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.13753756880760193},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10584887862205505},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10346898436546326},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2009.2017122","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2017122","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W178701193","https://openalex.org/W1758154469","https://openalex.org/W1759901977","https://openalex.org/W1836233800","https://openalex.org/W1979459774","https://openalex.org/W2003331958","https://openalex.org/W2012332625","https://openalex.org/W2040157947","https://openalex.org/W2047078096","https://openalex.org/W2115547150","https://openalex.org/W2118249800","https://openalex.org/W2122086266","https://openalex.org/W2126963487","https://openalex.org/W2127180804","https://openalex.org/W2129768577","https://openalex.org/W2144820986","https://openalex.org/W2425240487","https://openalex.org/W6607201821","https://openalex.org/W6638706860"],"related_works":["https://openalex.org/W2103645363","https://openalex.org/W2072989701","https://openalex.org/W2163580946","https://openalex.org/W1738647919","https://openalex.org/W2544864643","https://openalex.org/W2014443163","https://openalex.org/W2016594828","https://openalex.org/W2042607099","https://openalex.org/W614590117","https://openalex.org/W2166572289"],"abstract_inverted_index":{"Variable":[0],"block":[1,80,101],"size":[2],"motion":[3],"estimation":[4],"(VBSME)":[5],"is":[6,156,173,207],"one":[7,74],"of":[8,48,54,92,98,106,135,142,158],"several":[9],"contributors":[10],"to":[11,66,117,215],"H.264/AVC's":[12],"excellent":[13],"coding":[14],"efficiency.":[15],"However,":[16],"its":[17],"high":[18],"computational":[19],"complexity":[20],"and":[21,35,102,182],"huge":[22],"memory":[23,119,137,144],"traffic":[24],"make":[25],"deign":[26],"difficult.":[27],"In":[28],"this":[29],"paper,":[30],"we":[31,110],"propose":[32,111],"a":[33,64,87,99,112,148,192],"memory-efficient":[34],"highly":[36],"parallel":[37,69],"VLSI":[38],"architecture":[39,46,172],"for":[40,82,175,197],"full":[41],"search":[42,104,177],"VBSME":[43],"(FSVBSME).":[44],"Our":[45],"consists":[47,53],"16":[49,55,57],"2-D":[50],"arrays":[51,62],"each":[52],"\u00d7":[56,161],"processing":[58,159],"elements":[59],"(PEs).":[60],"Four":[61,77],"form":[63],"group":[65],"match":[67],"in":[68,86],"four":[70,83],"reference":[71,96,180],"blocks":[72,85,97],"against":[73],"current":[75,84,100,108],"block.":[76],"groups":[78],"perform":[79],"matching":[81],"pipelined":[88],"fashion.":[89],"Taking":[90],"advantage":[91],"overlapping":[93],"among":[94],"multiple":[95,179],"between":[103],"windows":[105],"adjacent":[107],"blocks,":[109],"novel":[113],"data":[114,127],"reuse":[115,128],"scheme":[116],"reduce":[118],"access.":[120],"Compared":[121],"with":[122,139],"the":[123,204,212],"popular":[124],"Level":[125],"C":[126],"scheme,":[129],"our":[130,154],"approach":[131],"can":[132],"save":[133],"98%":[134],"on-chip":[136],"access":[138],"only":[140],"25%":[141],"local":[143],"overhead.":[145],"Synthesized":[146],"into":[147],"TSMC":[149],"180-nm":[150],"CMOS":[151],"cell":[152],"library,":[153],"design":[155,195,206,214],"capable":[157],"1920":[160],"1088":[162],"30":[163],"fps":[164],"video":[165],"when":[166],"running":[167],"at":[168],"130":[169],"MHz.":[170],"The":[171],"scalable":[174],"wider":[176],"range,":[178],"frames":[181],"pixel":[183],"truncation":[184],"as":[185,187],"well":[186],"down":[188],"sampling.":[189],"We":[190],"suggest":[191],"criterion":[193],"called":[194],"efficiency":[196],"comparing":[198],"different":[199],"works.":[200],"It":[201],"shows":[202],"that":[203],"proposed":[205],"72%":[208],"more":[209],"efficient":[210],"than":[211],"best":[213],"date.":[216]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":4},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}