{"id":"https://openalex.org/W2110722828","doi":"https://doi.org/10.1109/tvlsi.2009.2013983","title":"IEEE Standard 1500 Compatible Delay Test Framework","display_name":"IEEE Standard 1500 Compatible Delay Test Framework","publication_year":2009,"publication_date":"2009-04-28","ids":{"openalex":"https://openalex.org/W2110722828","doi":"https://doi.org/10.1109/tvlsi.2009.2013983","mag":"2110722828"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2009.2013983","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2013983","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100629023","display_name":"Po\u2010Lin Chen","orcid":"https://orcid.org/0000-0002-4015-1052"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Po-Lin Chen","raw_affiliation_strings":["Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]},{"raw_affiliation_string":"Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan#TAB#","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108094010","display_name":"Jhih-Wei Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jhih-Wei Lin","raw_affiliation_strings":["Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]},{"raw_affiliation_string":"Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan#TAB#","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100885664","display_name":"Tsin\u2010Yuan Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Tsin-Yuan Chang","raw_affiliation_strings":["Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]},{"raw_affiliation_string":"Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan#TAB#","institution_ids":["https://openalex.org/I25846049"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.8043,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.7410106,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"17","issue":"8","first_page":"1152","last_page":"1156"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6603956818580627},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6258049011230469},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.6179423332214355},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.5997759103775024},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5142109394073486},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.4890371263027191},{"id":"https://openalex.org/keywords/test-method","display_name":"Test method","score":0.4658397436141968},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.4611068367958069},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32714831829071045},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21814227104187012},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.14373424649238586},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.06234738230705261}],"concepts":[{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6603956818580627},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6258049011230469},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.6179423332214355},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.5997759103775024},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5142109394073486},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4890371263027191},{"id":"https://openalex.org/C132519959","wikidata":"https://www.wikidata.org/wiki/Q3077373","display_name":"Test method","level":2,"score":0.4658397436141968},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.4611068367958069},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32714831829071045},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21814227104187012},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.14373424649238586},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.06234738230705261},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2009.2013983","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2013983","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1837496673","https://openalex.org/W1849928240","https://openalex.org/W1893733296","https://openalex.org/W1966905738","https://openalex.org/W2020550579","https://openalex.org/W2104548962","https://openalex.org/W2106100968","https://openalex.org/W2148250222","https://openalex.org/W2155288938","https://openalex.org/W2156203118","https://openalex.org/W2162086806","https://openalex.org/W2170533364"],"related_works":["https://openalex.org/W2131559056","https://openalex.org/W4254560580","https://openalex.org/W2127167802","https://openalex.org/W2080984854","https://openalex.org/W2323083271","https://openalex.org/W1576317492","https://openalex.org/W2065289416","https://openalex.org/W2017236304","https://openalex.org/W2115579119","https://openalex.org/W2136854845"],"abstract_inverted_index":{"Rapid":[0],"advances":[1],"in":[2,11,34],"semiconductor":[3],"technology":[4],"have":[5],"made":[6],"timing-related":[7],"defects":[8],"increasingly":[9],"crucial":[10],"core-based":[12,111],"system-on-chip":[13,35],"designs.":[14],"Currently,":[15],"modular":[16],"test":[17,27,62,67,73,83,95,101,133],"strategies":[18],"based":[19],"on":[20],"IEEE":[21],"standard":[22],"1500":[23],"are":[24],"applied":[25,89],"to":[26,40,49,77,93,127],"the":[28,42,65,70,91,98,119,124],"functionality":[29],"of":[30,53,58,105,110],"each":[31],"embedded":[32,60,71,81],"core":[33],"(SoC)":[36],"designs":[37],"but":[38],"fail":[39],"verify":[41],"corresponding":[43],"timing":[44],"specifications.":[45],"In":[46],"this":[47],"paper,":[48],"achieve":[50],"high":[51],"quality":[52,134],"delay":[54,61,72,82,100,112,120],"tests,":[55],"hardware":[56],"implementation":[57],"an":[59,79],"framework":[63,102,126],"including":[64],"modified":[66],"wrappers":[68],"and":[69,135],"mechanism":[74],"is":[75,88,103],"presented":[76],"build":[78],"entirely":[80],"environment":[84],"where":[85],"at-speed":[86],"clock":[87],"inside":[90],"chip":[92],"increase":[94],"accuracy.":[96],"Additionally,":[97],"proposed":[99,125],"capable":[104],"supporting":[106],"all":[107],"current":[108],"solutions":[109],"test.":[113],"The":[114],"experimental":[115],"results":[116],"successfully":[117],"demonstrate":[118],"testing":[121],"application":[122],"using":[123],"a":[128],"crypto":[129],"processor":[130],"with":[131],"satisfying":[132],"effectiveness.":[136]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
