{"id":"https://openalex.org/W2117853355","doi":"https://doi.org/10.1109/tvlsi.2009.2013397","title":"Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping","display_name":"Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping","publication_year":2009,"publication_date":"2009-04-15","ids":{"openalex":"https://openalex.org/W2117853355","doi":"https://doi.org/10.1109/tvlsi.2009.2013397","mag":"2117853355"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2009.2013397","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2013397","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101735061","display_name":"Hiroshi Sasaki","orcid":"https://orcid.org/0000-0001-7221-0742"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"H. Sasaki","raw_affiliation_strings":["Research Center of Advanced Science and Technology RCAST, University of Tokyo, Tokyo, Japan","Res. Center for Adv. Sci. & Technol. (RCAST), Univ. of Tokyo, Tokyo"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Research Center of Advanced Science and Technology RCAST, University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"Res. Center for Adv. Sci. & Technol. (RCAST), Univ. of Tokyo, Tokyo","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103017591","display_name":"Masaaki Kondo","orcid":"https://orcid.org/0000-0002-6025-8738"},"institutions":[{"id":"https://openalex.org/I20529979","display_name":"University of Electro-Communications","ror":"https://ror.org/02x73b849","country_code":"JP","type":"education","lineage":["https://openalex.org/I20529979"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Kondo","raw_affiliation_strings":["Graduate School of Information Systems, University of Electro-Communications, Tokyo, Japan","Grad. Sch. of Inf. Syst., Univ. of Electro-Commun., Chofu"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information Systems, University of Electro-Communications, Tokyo, Japan","institution_ids":["https://openalex.org/I20529979"]},{"raw_affiliation_string":"Grad. Sch. of Inf. Syst., Univ. of Electro-Commun., Chofu","institution_ids":["https://openalex.org/I20529979"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090578339","display_name":"Hiroshi Nakamura","orcid":"https://orcid.org/0009-0005-6505-1903"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"H. Nakamura","raw_affiliation_strings":["Research Center of Advanced Science and Technology RCAST, University of Tokyo, Tokyo, Japan","Res. Center for Adv. Sci. & Technol. (RCAST), Univ. of Tokyo, Tokyo"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Research Center of Advanced Science and Technology RCAST, University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"Res. Center for Adv. Sci. & Technol. (RCAST), Univ. of Tokyo, Tokyo","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2636,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.58659326,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"17","issue":"6","first_page":"848","last_page":"852"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7872248888015747},{"id":"https://openalex.org/keywords/instruction-scheduling","display_name":"Instruction scheduling","score":0.764186680316925},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.6256208419799805},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.5598517656326294},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5483260750770569},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.520839512348175},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.502753734588623},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4254264235496521},{"id":"https://openalex.org/keywords/instructions-per-cycle","display_name":"Instructions per cycle","score":0.41062772274017334},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35865747928619385},{"id":"https://openalex.org/keywords/rate-monotonic-scheduling","display_name":"Rate-monotonic scheduling","score":0.22404751181602478},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.1645096242427826},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.12296321988105774},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11283260583877563},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.1085958182811737},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10857987403869629},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08077466487884521}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7872248888015747},{"id":"https://openalex.org/C73564150","wikidata":"https://www.wikidata.org/wiki/Q11417093","display_name":"Instruction scheduling","level":5,"score":0.764186680316925},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.6256208419799805},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.5598517656326294},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5483260750770569},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.520839512348175},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.502753734588623},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4254264235496521},{"id":"https://openalex.org/C156972235","wikidata":"https://www.wikidata.org/wiki/Q1443434","display_name":"Instructions per cycle","level":3,"score":0.41062772274017334},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35865747928619385},{"id":"https://openalex.org/C127456818","wikidata":"https://www.wikidata.org/wiki/Q238879","display_name":"Rate-monotonic scheduling","level":4,"score":0.22404751181602478},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.1645096242427826},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.12296321988105774},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11283260583877563},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.1085958182811737},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10857987403869629},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08077466487884521},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2009.2013397","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2009.2013397","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.9100000262260437,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1584321010","https://openalex.org/W1989569696","https://openalex.org/W2032755892","https://openalex.org/W2102727118","https://openalex.org/W2104225326","https://openalex.org/W2108039095","https://openalex.org/W2117285153","https://openalex.org/W2121539621","https://openalex.org/W2122343863","https://openalex.org/W2143032080","https://openalex.org/W2148570943","https://openalex.org/W2156174665","https://openalex.org/W2161046276","https://openalex.org/W2161864047","https://openalex.org/W2535965777","https://openalex.org/W3140903683","https://openalex.org/W4236892585","https://openalex.org/W4237273530","https://openalex.org/W4242771098","https://openalex.org/W4249006057","https://openalex.org/W4253906885","https://openalex.org/W6658522515","https://openalex.org/W6676357615","https://openalex.org/W6677665269","https://openalex.org/W6682166583","https://openalex.org/W6792941224"],"related_works":["https://openalex.org/W122453572","https://openalex.org/W2027935151","https://openalex.org/W2351011383","https://openalex.org/W2146879484","https://openalex.org/W4221002079","https://openalex.org/W2162875803","https://openalex.org/W1757458251","https://openalex.org/W3081116756","https://openalex.org/W2154160953","https://openalex.org/W2112915496"],"abstract_inverted_index":{"Dynamic":[0],"instruction":[1,35,98],"scheduling":[2,36,99],"logic":[3],"is":[4],"quite":[5],"complex":[6],"and":[7,16,29,49,56,68,75],"dissipates":[8],"significant":[9],"energy":[10,30,73,87],"in":[11],"microprocessors":[12],"that":[13,80],"support":[14],"superscalar":[15],"out-of-order":[17],"execution.":[18],"We":[19],"propose":[20],"a":[21,45],"novel":[22],"microarchitectural":[23],"technique":[24,83],"to":[25,94],"reduce":[26,86],"the":[27,33,51,57,60,65,81,95],"complexity":[28],"consumption":[31],"of":[32,54,59],"dynamic":[34,97],"logic.":[37,100],"The":[38],"proposed":[39,82],"method":[40],"groups":[41],"several":[42],"instructions":[43],"as":[44],"single":[46],"issue":[47],"unit":[48],"reduces":[50],"required":[52],"number":[53],"ports":[55],"size":[58],"structure.":[61],"This":[62],"paper":[63],"describes":[64],"microarchitecture":[66],"mechanisms":[67],"shows":[69],"evaluation":[70],"results":[71,78],"for":[72],"savings":[74],"performance.":[76],"These":[77],"reveal":[79],"can":[84],"greatly":[85],"with":[88],"almost":[89],"no":[90],"performance":[91],"degradation,":[92],"compared":[93],"conventional":[96]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}