{"id":"https://openalex.org/W2098044033","doi":"https://doi.org/10.1109/tvlsi.2008.2009453","title":"A Novel Overlap-Based Logic Cell: An Efficient Implementation of Flip\u2013Flops With Embedded Logic","display_name":"A Novel Overlap-Based Logic Cell: An Efficient Implementation of Flip\u2013Flops With Embedded Logic","publication_year":2009,"publication_date":"2009-04-08","ids":{"openalex":"https://openalex.org/W2098044033","doi":"https://doi.org/10.1109/tvlsi.2008.2009453","mag":"2098044033"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2008.2009453","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2009453","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007969269","display_name":"O. Sarbishei","orcid":"https://orcid.org/0000-0001-5677-2462"},"institutions":[{"id":"https://openalex.org/I133529467","display_name":"Sharif University of Technology","ror":"https://ror.org/024c2fq17","country_code":"IR","type":"education","lineage":["https://openalex.org/I133529467"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Omid Sarbishei","raw_affiliation_strings":["Electrical Engineering Department, Sharif University of Technology, Tehran, Iran","Electr. Eng. Dept., Sharif Univ. of Technol., Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, Sharif University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I133529467"]},{"raw_affiliation_string":"Electr. Eng. Dept., Sharif Univ. of Technol., Tehran, Iran","institution_ids":["https://openalex.org/I133529467"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040073771","display_name":"Mohammad Maymandi\u2010Nejad","orcid":"https://orcid.org/0000-0002-8592-7416"},"institutions":[{"id":"https://openalex.org/I86958956","display_name":"Ferdowsi University of Mashhad","ror":"https://ror.org/00g6ka752","country_code":"IR","type":"education","lineage":["https://openalex.org/I86958956"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Mohammad Maymandi-Nejad","raw_affiliation_strings":["Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran","Dept. of Electr. Eng., Ferdowsi Univ. of Mashhad, Mashhad, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran","institution_ids":["https://openalex.org/I86958956"]},{"raw_affiliation_string":"Dept. of Electr. Eng., Ferdowsi Univ. of Mashhad, Mashhad, Iran","institution_ids":["https://openalex.org/I86958956"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3052,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.63804794,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"18","issue":"2","first_page":"222","last_page":"231"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6800221800804138},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6405315399169922},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.6167620420455933},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6113767623901367},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5942378640174866},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5592538118362427},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.5301868319511414},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.4850544333457947},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4643920063972473},{"id":"https://openalex.org/keywords/dynamic-logic","display_name":"Dynamic logic (digital electronics)","score":0.45105424523353577},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4360157251358032},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3994661569595337},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3982802629470825},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.364780455827713},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.324741929769516},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2814362645149231},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17763692140579224},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.17036086320877075},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.12980139255523682},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.11931809782981873},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.0853273868560791}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6800221800804138},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6405315399169922},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.6167620420455933},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6113767623901367},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5942378640174866},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5592538118362427},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.5301868319511414},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.4850544333457947},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4643920063972473},{"id":"https://openalex.org/C2777796570","wikidata":"https://www.wikidata.org/wiki/Q2351326","display_name":"Dynamic logic (digital electronics)","level":4,"score":0.45105424523353577},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4360157251358032},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3994661569595337},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3982802629470825},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.364780455827713},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.324741929769516},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2814362645149231},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17763692140579224},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.17036086320877075},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.12980139255523682},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.11931809782981873},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0853273868560791}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2008.2009453","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2009453","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.989.8329","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.989.8329","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://profdoc.um.ac.ir/articles/a/1014043.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8799999952316284,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321157","display_name":"Sharif University of Technology","ror":"https://ror.org/024c2fq17"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1966105053","https://openalex.org/W2005908631","https://openalex.org/W2010111173","https://openalex.org/W2046641314","https://openalex.org/W2061528230","https://openalex.org/W2063073439","https://openalex.org/W2085822974","https://openalex.org/W2085962397","https://openalex.org/W2097015933","https://openalex.org/W2097081065","https://openalex.org/W2098560323","https://openalex.org/W2109195618","https://openalex.org/W2127696501","https://openalex.org/W2130603692","https://openalex.org/W2137616964","https://openalex.org/W2153077879","https://openalex.org/W2168350974","https://openalex.org/W2168675153","https://openalex.org/W4243164749","https://openalex.org/W6674299193","https://openalex.org/W6682831697","https://openalex.org/W6685231212"],"related_works":["https://openalex.org/W2155174752","https://openalex.org/W1593362825","https://openalex.org/W2991771859","https://openalex.org/W2158157809","https://openalex.org/W21585740","https://openalex.org/W3122224509","https://openalex.org/W2127151832","https://openalex.org/W3042080464","https://openalex.org/W2136656113","https://openalex.org/W2118487491"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"several":[3,55],"efficient":[4,87,109],"architectures":[5],"of":[6,26,29,37,91],"dynamic/static":[7,57],"edge-triggered":[8],"flip-flops":[9],"with":[10,54],"a":[11,62],"compact":[12],"embedded":[13,93],"logic.":[14],"The":[15,34,48,75],"proposed":[16,49],"structure,":[17],"which":[18,104],"benefits":[19],"from":[20],"the":[21,27,30,39,80,89],"overlap":[22,41],"period,":[23],"fixes":[24],"most":[25],"drawbacks":[28],"dynamic":[31],"logic":[32,58,82,94],"family.":[33],"design":[35],"issues":[36],"setting":[38],"appropriate":[40],"period":[42],"for":[43],"this":[44,98],"architecture":[45],"are":[46],"explained.":[47],"overlap-based":[50,81],"approach":[51,99],"is":[52],"compared":[53],"state-of-the-art":[56],"styles":[59],"in":[60,110],"implementing":[61],"4-bit":[63],"shift":[64],"register":[65],"and":[66],"an":[67],"odd-even":[68],"sort":[69],"coprocessor":[70],"using":[71],"different":[72],"CMOS":[73,114],"technologies.":[74,115],"simulation":[76],"results":[77],"showed":[78],"that":[79],"cells":[83],"become":[84],"much":[85],"more":[86,108],"when":[88],"complexity":[90],"their":[92],"function":[95],"increases.":[96],"Moreover,":[97],"improves":[100],"static":[101],"power":[102],"consumption,":[103],"makes":[105],"it":[106],"even":[107],"below":[111],"0.18":[112],"\u00bfm":[113]},"counts_by_year":[{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":6},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}