{"id":"https://openalex.org/W2098750459","doi":"https://doi.org/10.1109/tvlsi.2008.2008453","title":"Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating","display_name":"Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating","publication_year":2008,"publication_date":"2008-12-10","ids":{"openalex":"https://openalex.org/W2098750459","doi":"https://doi.org/10.1109/tvlsi.2008.2008453","mag":"2098750459"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2008.2008453","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2008453","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066983905","display_name":"Hamid Mahmoodi","orcid":"https://orcid.org/0000-0003-4237-3086"},"institutions":[{"id":"https://openalex.org/I71838634","display_name":"San Francisco State University","ror":"https://ror.org/05ykr0121","country_code":"US","type":"education","lineage":["https://openalex.org/I71838634"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"H. Mahmoodi","raw_affiliation_strings":["Department of Electrical and Computer Engineering School of Engineering, San Francisco State University, San Francisco, CA, USA","Dept. of Electr. & Comput. Eng., San Francisco State Univ., San Francisco, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering School of Engineering, San Francisco State University, San Francisco, CA, USA","institution_ids":["https://openalex.org/I71838634"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., San Francisco State Univ., San Francisco, CA","institution_ids":["https://openalex.org/I71838634"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052928612","display_name":"Vishwanadh Tirumalashetty","orcid":null},"institutions":[{"id":"https://openalex.org/I157288922","display_name":"Itron (United States)","ror":"https://ror.org/01851c371","country_code":"US","type":"company","lineage":["https://openalex.org/I157288922"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"V. Tirumalashetty","raw_affiliation_strings":["Itron, Inc., Oakland, CA, USA","Itron Inc., Oakland, CA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Itron, Inc., Oakland, CA, USA","institution_ids":["https://openalex.org/I157288922"]},{"raw_affiliation_string":"Itron Inc., Oakland, CA#TAB#","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102941840","display_name":"Matthew Cooke","orcid":"https://orcid.org/0000-0003-0964-2715"},"institutions":[{"id":"https://openalex.org/I4210137977","display_name":"Advanced Micro Devices (United States)","ror":"https://ror.org/04kd6c783","country_code":"US","type":"company","lineage":["https://openalex.org/I4210137977"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Cooke","raw_affiliation_strings":["Advanced Micro Devices, Inc., Austin, TX, USA","AMD, Austin, TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Micro Devices, Inc., Austin, TX, USA","institution_ids":["https://openalex.org/I4210137977"]},{"raw_affiliation_string":"AMD, Austin, TX","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031161187","display_name":"Kaushik Roy","orcid":"https://orcid.org/0000-0002-0735-9695"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Roy","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":7.1234,"has_fulltext":false,"cited_by_count":161,"citation_normalized_percentile":{"value":0.97170952,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":91,"max":100},"biblio":{"volume":"17","issue":"1","first_page":"33","last_page":"44"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.9042665958404541},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.6752350926399231},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.6200594305992126},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.5721639394760132},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5596550703048706},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.5331306457519531},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.502368688583374},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.4948808550834656},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.4910125732421875},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.44607970118522644},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.4460076093673706},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4307302236557007},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.4063093066215515},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.302717924118042},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.18564945459365845},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.11394456028938293}],"concepts":[{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.9042665958404541},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.6752350926399231},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.6200594305992126},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.5721639394760132},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5596550703048706},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.5331306457519531},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.502368688583374},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.4948808550834656},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.4910125732421875},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.44607970118522644},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.4460076093673706},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4307302236557007},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.4063093066215515},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.302717924118042},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.18564945459365845},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.11394456028938293},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2008.2008453","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2008453","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9100000262260437,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1508731700","https://openalex.org/W1590076604","https://openalex.org/W1869147173","https://openalex.org/W1996086722","https://openalex.org/W2056378213","https://openalex.org/W2097015933","https://openalex.org/W2137310043","https://openalex.org/W2137616964","https://openalex.org/W2138831086","https://openalex.org/W2164002677","https://openalex.org/W2170191597","https://openalex.org/W2170265438","https://openalex.org/W3143002681","https://openalex.org/W6635350213","https://openalex.org/W6674450901"],"related_works":["https://openalex.org/W2474747038","https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W2137310043","https://openalex.org/W3006003651","https://openalex.org/W2337711143","https://openalex.org/W4313332229","https://openalex.org/W2090213929","https://openalex.org/W2617666058"],"abstract_inverted_index":{"A":[0],"significant":[1,44],"fraction":[2],"of":[3,98,107,135,230,245],"the":[4,39,64,101,114,118,158,171,181,201,205,219,233,248],"total":[5,104],"power":[6,96,105,165,176,228,243],"in":[7,43,170,180,240],"highly":[8],"synchronous":[9],"systems":[10],"is":[11,211],"dissipated":[12],"over":[13],"clock":[14,40,80,128,137,146,155],"networks.":[15],"Hence,":[16],"low-power":[17,24],"clocking":[18,121,222],"schemes":[19],"are":[20],"promising":[21],"approaches":[22],"for":[23,130,149,247],"design.":[25],"We":[26],"propose":[27,145],"four":[28],"novel":[29],"energy":[30,36,45,73,131,150,159,207,220],"recovery":[31,37,74,132,151,160,208,221],"clocked":[32,75,161,198,209],"flip-flops":[33,49,76,162,199,210,225],"that":[34],"enable":[35],"from":[38],"network,":[41],"resulting":[42,239],"savings.":[46],"The":[47],"proposed":[48,72,206],"operate":[50],"with":[51,60,174,194,204],"a":[52,84,89,95,126,185,227],"single-phase":[53],"sinusoidal":[54,90,127],"clock,":[55],"which":[56],"can":[57],"be":[58],"generated":[59],"high":[61],"efficiency.":[62],"In":[63,140],"TSMC":[65],"0.25-mum":[66],"CMOS":[67],"technology,":[68],"we":[69,143],"implemented":[70],"1024":[71],"through":[77],"an":[78,241],"H-tree":[79],"network":[81],"driven":[82],"by":[83,166],"resonant":[85],"clock-generator":[86],"to":[87,109,113,157],"generate":[88],"clock.":[91],"Simulation":[92],"results":[93],"show":[94,226],"reduction":[97,229],"90%":[99],"on":[100,216,232,237],"clock-tree":[102,234],"and":[103,123,177,200,213,224,235],"savings":[106,244],"up":[108],"83%":[110],"as":[111],"compared":[112],"same":[115],"implementation":[116],"using":[117],"conventional":[119,195],"square-wave":[120],"scheme":[122,223],"flip-flops.":[124],"Using":[125],"signal":[129],"prevents":[133],"application":[134],"existing":[136],"gating":[138,147,156],"solutions.":[139],"this":[141],"paper,":[142],"also":[144],"solutions":[148],"clocking.":[152],"Applying":[153],"our":[154],"reduces":[163],"their":[164],"more":[167],"than":[168],"1000times":[169],"idle":[172],"mode":[173],"negligible":[175],"delay":[178],"overhead":[179],"active":[182],"mode.":[183],"Finally,":[184],"test":[186],"chip":[187],"containing":[188],"two":[189],"pipelined":[190],"multipliers":[191],"one":[192,203],"designed":[193],"square":[196],"wave":[197],"other":[202],"fabricated":[212],"measured.":[214],"Based":[215],"measurement":[217],"results,":[218],"71%":[231],"39%":[236],"flip-flops,":[238],"overall":[242],"25%":[246],"multiplier":[249],"chip.":[250]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":10},{"year":2019,"cited_by_count":9},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":14},{"year":2016,"cited_by_count":11},{"year":2015,"cited_by_count":18},{"year":2014,"cited_by_count":35},{"year":2013,"cited_by_count":12},{"year":2012,"cited_by_count":10}],"updated_date":"2026-06-19T17:40:00.097472","created_date":"2025-10-10T00:00:00"}