{"id":"https://openalex.org/W2161776409","doi":"https://doi.org/10.1109/tvlsi.2008.2005309","title":"Power Management of Voltage/Frequency Island-Based Systems Using Hardware-Based Methods","display_name":"Power Management of Voltage/Frequency Island-Based Systems Using Hardware-Based Methods","publication_year":2009,"publication_date":"2009-02-09","ids":{"openalex":"https://openalex.org/W2161776409","doi":"https://doi.org/10.1109/tvlsi.2008.2005309","mag":"2161776409"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2008.2005309","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2005309","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112624616","display_name":"Puru Choudhary","orcid":null},"institutions":[{"id":"https://openalex.org/I4210154351","display_name":"Marvell (United States)","ror":"https://ror.org/04wmff902","country_code":"US","type":"company","lineage":["https://openalex.org/I4210092679","https://openalex.org/I4210154351"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"P. Choudhary","raw_affiliation_strings":["Marvell Semiconductor, Inc., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Marvell Semiconductor, Inc., Santa Clara, CA, USA","institution_ids":["https://openalex.org/I4210154351"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065985595","display_name":"Diana Marculescu","orcid":"https://orcid.org/0000-0002-5734-4221"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Marculescu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5112624616"],"corresponding_institution_ids":["https://openalex.org/I4210154351"],"apc_list":null,"apc_paid":null,"fwci":3.4839,"has_fulltext":false,"cited_by_count":42,"citation_normalized_percentile":{"value":0.93260767,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":"17","issue":"3","first_page":"427","last_page":"438"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6892114877700806},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6330040097236633},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6069733500480652},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.6025397181510925},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.5922132134437561},{"id":"https://openalex.org/keywords/workload","display_name":"Workload","score":0.5616419315338135},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.5295755863189697},{"id":"https://openalex.org/keywords/power-management","display_name":"Power management","score":0.4583297669887543},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.35661184787750244},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.33064109086990356},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.19901445508003235},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.103974848985672},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07861748337745667}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6892114877700806},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6330040097236633},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6069733500480652},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.6025397181510925},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.5922132134437561},{"id":"https://openalex.org/C2778476105","wikidata":"https://www.wikidata.org/wiki/Q628539","display_name":"Workload","level":2,"score":0.5616419315338135},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.5295755863189697},{"id":"https://openalex.org/C2778774385","wikidata":"https://www.wikidata.org/wiki/Q4437810","display_name":"Power management","level":3,"score":0.4583297669887543},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.35661184787750244},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.33064109086990356},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.19901445508003235},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.103974848985672},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07861748337745667},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2008.2005309","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2005309","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.158.3478","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.158.3478","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.cmu.edu/~dianam/journals/tvlsi09-1.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1978118906","https://openalex.org/W1978708760","https://openalex.org/W2053794660","https://openalex.org/W2108730429","https://openalex.org/W2110574557","https://openalex.org/W2117897741","https://openalex.org/W2127024907","https://openalex.org/W2130048908","https://openalex.org/W2131507936","https://openalex.org/W2134551980","https://openalex.org/W2140137324","https://openalex.org/W2142598547","https://openalex.org/W2145973680","https://openalex.org/W4234428373","https://openalex.org/W4239248797","https://openalex.org/W4245535903","https://openalex.org/W4245787350","https://openalex.org/W4248497301"],"related_works":["https://openalex.org/W986318368","https://openalex.org/W2000785801","https://openalex.org/W2384410913","https://openalex.org/W2352878646","https://openalex.org/W2990194547","https://openalex.org/W2731059981","https://openalex.org/W2070385207","https://openalex.org/W1967088250","https://openalex.org/W2291329885","https://openalex.org/W1987554710"],"abstract_inverted_index":{"Shrinking":[0],"technology":[1],"nodes":[2],"combined":[3],"with":[4],"the":[5,27,31,54,94,115,147,178,208,212,215,227,240],"need":[6],"for":[7,159,190,202,245],"higher":[8],"clock":[9,21,61],"speeds":[10],"have":[11,125,137,185],"made":[12],"it":[13,123],"increasingly":[14],"difficult":[15],"to":[16,71,91,113],"distribute":[17],"a":[18,23,49,85,100,107,118,173,187,191,219],"single":[19,174],"global":[20,57],"across":[22],"chip":[24],"while":[25,51,129,225],"meeting":[26],"power":[28,44,127,216],"requirements":[29],"of":[30,48,56,99,117,149,172,180,218,229],"design.":[32],"Globally":[33],"asynchronous":[34],"locally":[35],"synchronous":[36,119],"(GALS)":[37],"design":[38,50,161],"style":[39,162],"can":[40,64,169,221,242],"help":[41],"achieve":[42],"low":[43],"consumption":[45,217],"and":[46,96,144],"modularity":[47],"greatly":[52],"reducing":[53],"number":[55],"interconnects.":[58],"Such":[59,152],"multiple":[60],"domain":[62,73],"architectures":[63],"benefit":[65],"from":[66,207],"having":[67],"frequency/voltage":[68],"values":[69],"assigned":[70],"each":[72,203],"based":[74],"on":[75,236],"workload":[76],"requirements.":[77],"The":[78,205],"work":[79,233],"presented":[80],"in":[81,142,146],"this":[82],"paper":[83],"proposes":[84],"new":[86],"<i":[87],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[88],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">hardware-based</i>":[89],"approach":[90],"dynamically":[92],"change":[93,114],"frequencies":[95],"potentially":[97,222],"voltages":[98],"voltage-frequency":[101],"island":[102,120],"(VFI)":[103],"system":[104,189,220],"driven":[105],"by":[106],"dynamic":[108],"workload.":[109],"This":[110],"technique":[111],"tries":[112],"frequency":[116],"such":[121],"that":[122,197,214],"will":[124],"efficient":[126],"utilization":[128],"satisfying":[130],"performance":[131,228],"constraints.":[132],"In":[133],"recent":[134],"years,":[135],"there":[136],"been":[138],"major":[139],"developments,":[140],"both":[141],"industry":[143],"academia,":[145],"field":[148],"multiprocessor":[150,153,188],"systems.":[151],"systems":[154],"are":[155],"very":[156],"good":[157],"candidates":[158],"VFI":[160],"implementation,":[163],"where":[164],"one":[165],"or":[166],"more":[167],"processors":[168],"be":[170,223,243],"part":[171],"VFI.":[175],"To":[176],"demonstrate":[177],"feasibility":[179],"our":[181],"proposed":[182],"method,":[183],"we":[184],"implemented":[186],"field-programmable":[192],"gate":[193],"array":[194],"(FPGA)":[195],"platform":[196,210],"uses":[198],"independently":[199],"generated":[200],"clocks":[201],"processor.":[204],"results":[206],"FPGA":[209],"confirm":[211],"claim":[213],"reduced":[224],"maintaining":[226],"many":[230],"applications.":[231],"Our":[232],"concentrates":[234],"primarily":[235],"embedded":[237],"systems,":[238],"but":[239],"idea":[241],"explored":[244],"general-purpose":[246],"computing":[247],"as":[248],"well.":[249]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":8},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":5}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}