{"id":"https://openalex.org/W2142533150","doi":"https://doi.org/10.1109/tvlsi.2008.2005307","title":"Total Power Modeling in FPGAs Under Spatial Correlation","display_name":"Total Power Modeling in FPGAs Under Spatial Correlation","publication_year":2009,"publication_date":"2009-02-13","ids":{"openalex":"https://openalex.org/W2142533150","doi":"https://doi.org/10.1109/tvlsi.2008.2005307","mag":"2142533150"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2008.2005307","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2005307","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021823528","display_name":"Hossam Hassan","orcid":"https://orcid.org/0000-0003-3932-9009"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"H.A. Hassan","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Waterloo, Waterloo, ONT, Canada","Electr. & Comput. Eng. Dept, Univ. of Waterloo, Waterloo, ON"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Waterloo, Waterloo, ONT, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"Electr. & Comput. Eng. Dept, Univ. of Waterloo, Waterloo, ON","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112829693","display_name":"Mohab Anis","orcid":null},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"M. Anis","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Waterloo, Waterloo, ONT, Canada","Electr. & Comput. Eng. Dept, Univ. of Waterloo, Waterloo, ON"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Waterloo, Waterloo, ONT, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"Electr. & Comput. Eng. Dept, Univ. of Waterloo, Waterloo, ON","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111957282","display_name":"M. Elmasry","orcid":null},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"M. Elmasry","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Waterloo, Waterloo, ONT, Canada","Electr. & Comput. Eng. Dept, Univ. of Waterloo, Waterloo, ON"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Waterloo, Waterloo, ONT, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"Electr. & Comput. Eng. Dept, Univ. of Waterloo, Waterloo, ON","institution_ids":["https://openalex.org/I151746483"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9155,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.78364863,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"17","issue":"4","first_page":"578","last_page":"582"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8411798477172852},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.7275680899620056},{"id":"https://openalex.org/keywords/independence","display_name":"Independence (probability theory)","score":0.7153398990631104},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.576943576335907},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5762839913368225},{"id":"https://openalex.org/keywords/spatial-correlation","display_name":"Spatial correlation","score":0.5609458684921265},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.545875608921051},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4995768070220947},{"id":"https://openalex.org/keywords/dependency","display_name":"Dependency (UML)","score":0.495428204536438},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.47184041142463684},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4647926688194275},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2768669128417969},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22569549083709717},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21176666021347046},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1629287302494049},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1604454219341278},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.10545828938484192},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.09544309973716736},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08794820308685303}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8411798477172852},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.7275680899620056},{"id":"https://openalex.org/C35651441","wikidata":"https://www.wikidata.org/wiki/Q625303","display_name":"Independence (probability theory)","level":2,"score":0.7153398990631104},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.576943576335907},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5762839913368225},{"id":"https://openalex.org/C150060386","wikidata":"https://www.wikidata.org/wiki/Q7574054","display_name":"Spatial correlation","level":2,"score":0.5609458684921265},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.545875608921051},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4995768070220947},{"id":"https://openalex.org/C19768560","wikidata":"https://www.wikidata.org/wiki/Q320727","display_name":"Dependency (UML)","level":2,"score":0.495428204536438},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.47184041142463684},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4647926688194275},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2768669128417969},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22569549083709717},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21176666021347046},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1629287302494049},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1604454219341278},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.10545828938484192},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.09544309973716736},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08794820308685303},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2008.2005307","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2005307","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1719300925","https://openalex.org/W2096424065","https://openalex.org/W2111589882","https://openalex.org/W2118014020","https://openalex.org/W2125469204","https://openalex.org/W2137917061","https://openalex.org/W2141070498","https://openalex.org/W2141248063","https://openalex.org/W2148837165","https://openalex.org/W2150548722","https://openalex.org/W2160952696","https://openalex.org/W2166597372","https://openalex.org/W2170510975","https://openalex.org/W3148651068","https://openalex.org/W3149866969","https://openalex.org/W4231351310","https://openalex.org/W4232411756","https://openalex.org/W4232911756","https://openalex.org/W6637449779"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W3042736233","https://openalex.org/W2067317451","https://openalex.org/W2082487009","https://openalex.org/W4211085505","https://openalex.org/W2373535795","https://openalex.org/W2406926880"],"abstract_inverted_index":{"This":[0],"work":[1],"describes":[2],"a":[3],"novel":[4],"approach":[5],"for":[6,62],"total":[7],"power":[8,39,47,63,72,85,102],"estimation":[9,73,86],"in":[10,23,49,104],"field-programmable":[11],"gate":[12],"arrays":[13],"(FPGAs)":[14],"while":[15],"considering":[16],"spatial":[17,30,90,97],"correlation":[18],"among":[19],"the":[20,24,37,42,45,50,58,70,96],"different":[21],"signals":[22],"design.":[25],"The":[26,67],"signal":[27],"probabilities":[28],"under":[29],"correlations":[31],"are":[32],"used":[33],"to":[34,65],"properly":[35],"model":[36,60],"dynamic":[38],"dissipation":[40,48,103],"and":[41,52,82],"state-dependency":[43],"of":[44,55,69,79,109],"leakage":[46],"logic":[51],"routing":[53],"resources":[54],"FPGAs.":[56],"Moreover,":[57],"proposed":[59],"accounts":[61],"due":[64],"glitches.":[66],"accuracy":[68],"developed":[71],"technique":[74],"is":[75,93],"compared":[76],"with":[77],"that":[78,88,95],"HSpice":[80],"simulations":[81],"other":[83],"FPGA":[84],"techniques":[87],"assume":[89],"independence.":[91],"It":[92],"found":[94],"independence":[98],"assumption":[99],"can":[100],"overestimate":[101],"FPGAs":[105],"by":[106],"an":[107],"average":[108],"19%.":[110]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
