{"id":"https://openalex.org/W2114650941","doi":"https://doi.org/10.1109/tvlsi.2008.2004482","title":"The ARISE Approach for Extending Embedded Processors With Arbitrary Hardware Accelerators","display_name":"The ARISE Approach for Extending Embedded Processors With Arbitrary Hardware Accelerators","publication_year":2009,"publication_date":"2009-01-16","ids":{"openalex":"https://openalex.org/W2114650941","doi":"https://doi.org/10.1109/tvlsi.2008.2004482","mag":"2114650941"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2008.2004482","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2004482","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014728553","display_name":"Nikolaos Vassiliadis","orcid":null},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"N. Vassiliadis","raw_affiliation_strings":["Electronics and Computers Section, Physics Department, Aristotle University of Thessaloniki, Thessaloniki, Greece","Phys. Dept., Aristotle Univ. of Thessaloniki, Thessaloniki"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics and Computers Section, Physics Department, Aristotle University of Thessaloniki, Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]},{"raw_affiliation_string":"Phys. Dept., Aristotle Univ. of Thessaloniki, Thessaloniki","institution_ids":["https://openalex.org/I21370196"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006492102","display_name":"Georgios Theodoridis","orcid":"https://orcid.org/0000-0002-2015-108X"},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"G. Theodoridis","raw_affiliation_strings":["Electronics and Computers Section, Physics Department, Aristotle University of Thessaloniki, Thessaloniki, Greece","Phys. Dept., Aristotle Univ. of Thessaloniki, Thessaloniki"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics and Computers Section, Physics Department, Aristotle University of Thessaloniki, Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]},{"raw_affiliation_string":"Phys. Dept., Aristotle Univ. of Thessaloniki, Thessaloniki","institution_ids":["https://openalex.org/I21370196"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023894427","display_name":"S. Nikolaidis","orcid":"https://orcid.org/0000-0002-9794-8062"},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"S. Nikolaidis","raw_affiliation_strings":["Electronics and Computers Section, Physics Department, Aristotle University of Thessaloniki, Thessaloniki, Greece","Phys. Dept., Aristotle Univ. of Thessaloniki, Thessaloniki"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics and Computers Section, Physics Department, Aristotle University of Thessaloniki, Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]},{"raw_affiliation_string":"Phys. Dept., Aristotle Univ. of Thessaloniki, Thessaloniki","institution_ids":["https://openalex.org/I21370196"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I21370196"],"apc_list":null,"apc_paid":null,"fwci":2.3722,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.89143244,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"17","issue":"2","first_page":"221","last_page":"233"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8270094394683838},{"id":"https://openalex.org/keywords/coprocessor","display_name":"Coprocessor","score":0.6952568292617798},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6563311219215393},{"id":"https://openalex.org/keywords/opcode","display_name":"Opcode","score":0.6560796499252319},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6027374863624573},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.5956145524978638},{"id":"https://openalex.org/keywords/application-specific-instruction-set-processor","display_name":"Application-specific instruction-set processor","score":0.5622661709785461},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5352789759635925},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5200642943382263},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5091339945793152},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.5049269795417786},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.45913511514663696},{"id":"https://openalex.org/keywords/operand","display_name":"Operand","score":0.45274221897125244},{"id":"https://openalex.org/keywords/porting","display_name":"Porting","score":0.44276875257492065},{"id":"https://openalex.org/keywords/microcode","display_name":"Microcode","score":0.44121283292770386},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4411585032939911},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.20995745062828064},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13143354654312134},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.11097776889801025}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8270094394683838},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.6952568292617798},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6563311219215393},{"id":"https://openalex.org/C52173422","wikidata":"https://www.wikidata.org/wiki/Q766483","display_name":"Opcode","level":2,"score":0.6560796499252319},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6027374863624573},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.5956145524978638},{"id":"https://openalex.org/C201736964","wikidata":"https://www.wikidata.org/wiki/Q621583","display_name":"Application-specific instruction-set processor","level":3,"score":0.5622661709785461},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5352789759635925},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5200642943382263},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5091339945793152},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.5049269795417786},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.45913511514663696},{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.45274221897125244},{"id":"https://openalex.org/C106251023","wikidata":"https://www.wikidata.org/wiki/Q851989","display_name":"Porting","level":3,"score":0.44276875257492065},{"id":"https://openalex.org/C22174128","wikidata":"https://www.wikidata.org/wiki/Q175869","display_name":"Microcode","level":2,"score":0.44121283292770386},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4411585032939911},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.20995745062828064},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13143354654312134},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.11097776889801025},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2008.2004482","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2004482","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5699999928474426}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":38,"referenced_works":["https://openalex.org/W286049110","https://openalex.org/W1686420892","https://openalex.org/W1997179893","https://openalex.org/W2023426888","https://openalex.org/W2025787141","https://openalex.org/W2034841960","https://openalex.org/W2043785486","https://openalex.org/W2048586388","https://openalex.org/W2075921636","https://openalex.org/W2082329391","https://openalex.org/W2096820905","https://openalex.org/W2098129944","https://openalex.org/W2098363613","https://openalex.org/W2103581911","https://openalex.org/W2124178168","https://openalex.org/W2124813728","https://openalex.org/W2131442634","https://openalex.org/W2135050419","https://openalex.org/W2138149471","https://openalex.org/W2143065037","https://openalex.org/W2146188244","https://openalex.org/W2155509874","https://openalex.org/W2156589477","https://openalex.org/W2163689494","https://openalex.org/W2165099691","https://openalex.org/W2168569016","https://openalex.org/W2173674295","https://openalex.org/W2535965777","https://openalex.org/W2537134123","https://openalex.org/W3013416190","https://openalex.org/W3146150975","https://openalex.org/W3151159671","https://openalex.org/W4234019802","https://openalex.org/W4239692940","https://openalex.org/W4242272245","https://openalex.org/W4250370106","https://openalex.org/W4250486818","https://openalex.org/W6637151178"],"related_works":["https://openalex.org/W4253086129","https://openalex.org/W2105427843","https://openalex.org/W4251305139","https://openalex.org/W1967153778","https://openalex.org/W2052027147","https://openalex.org/W2154122810","https://openalex.org/W3022059713","https://openalex.org/W2391265499","https://openalex.org/W4229504459","https://openalex.org/W1574275277"],"abstract_inverted_index":{"ARISE":[0,74,173,207],"introduces":[1],"a":[2,29,32,40,104,112,115,146,168,179,201,221],"systematic":[3],"approach":[4],"for":[5,54,66],"extending":[6],"once":[7,125],"an":[8,17,141],"embedded":[9,142],"processor":[10,113,131,158,170,194],"to":[11,140,220],"support":[12,99],"thereafter":[13],"the":[14,49,58,60,84,109,121,126,130,151,157,160,172,189,193,206],"coupling":[15],"of":[16,20,45,52,57,96,111,117,129,192,203],"arbitrary":[18],"number":[19],"custom":[21],"computing":[22],"units":[23],"(CCUs).":[24],"A":[25],"CCU":[26],"can":[27,36],"be":[28,37],"hardwired":[30],"or":[31],"reconfigurable":[33],"unit,":[34],"which":[35],"utilized":[38],"following":[39],"tight":[41],"and/or":[42],"loose":[43],"model":[44,51,191],"computation.":[46],"By":[47],"selecting":[48],"appropriate":[50],"computation":[53],"each":[55],"part":[56],"application,":[59],"complete":[61],"application":[62],"space":[63,86],"is":[64,80,195],"considered":[65],"acceleration,":[67],"resulting":[68],"in":[69,93],"significant":[70,213],"performance":[71],"improvements.":[72],"Also,":[73,198],"offers":[75],"modularity":[76],"and":[77,79,87,114,153,159,175,215],"scalability":[78],"not":[81,196],"restricted":[82],"by":[83],"opcode":[85],"operands":[88],"limitation":[89],"problems":[90],"that":[91,107,149,188],"exist":[92],"such":[94],"type":[95],"machines.":[97],"To":[98,119,135,162],"these":[100,138],"features":[101,139],"we":[102,123,144,166,199],"introduce":[103],"machine":[105],"organization":[106],"allows":[108],"cooperation":[110],"set":[116,128,202],"CCUs.":[118,161],"control":[120,152],"CCUs":[122],"extend":[124],"instruction":[127],"with":[132,171],"eight":[133],"instructions.":[134],"efficiently":[136],"incorporate":[137],"processor,":[143],"propose":[145],"micro-architecture":[147],"implementation":[148],"minimizes":[150],"communication":[154,217],"overhead":[155,218],"between":[156],"evaluate":[163],"our":[164],"proposal,":[165],"extended":[167],"MIPS":[169],"infrastructure":[174],"implemented":[176,200],"it":[177],"on":[178,205],"Xilinx":[180],"field-programmable":[181],"gate":[182],"array":[183],"(FPGA).":[184],"Implementation":[185],"results,":[186],"demonstrate":[187],"timing":[190],"affected.":[197],"benchmarks":[204],"evaluation":[208],"machine.":[209],"Performance":[210],"results":[211],"prove":[212],"improvements":[214],"reduced":[216],"compared":[219],"typical":[222],"coprocessor":[223],"approach.":[224]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}