{"id":"https://openalex.org/W2096686240","doi":"https://doi.org/10.1109/tvlsi.2008.2003517","title":"Analog Automatic Test Pattern Generation for Quasi-Static Structural Test","display_name":"Analog Automatic Test Pattern Generation for Quasi-Static Structural Test","publication_year":2009,"publication_date":"2009-03-19","ids":{"openalex":"https://openalex.org/W2096686240","doi":"https://doi.org/10.1109/tvlsi.2008.2003517","mag":"2096686240"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2008.2003517","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2003517","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://pure.tue.nl/ws/files/3305960/Metis231262.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019444861","display_name":"Amir Zjajo","orcid":"https://orcid.org/0000-0002-0716-8186"},"institutions":[{"id":"https://openalex.org/I109147379","display_name":"NXP (Netherlands)","ror":"https://ror.org/059be4e97","country_code":"NL","type":"company","lineage":["https://openalex.org/I109147379"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"A. Zjajo","raw_affiliation_strings":["NXP Semiconductors, Eindhoven, Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NXP Semiconductors, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I109147379"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050945839","display_name":"Jos\u00e9 Pineda de Gyvez","orcid":"https://orcid.org/0000-0002-0723-7065"},"institutions":[{"id":"https://openalex.org/I109147379","display_name":"NXP (Netherlands)","ror":"https://ror.org/059be4e97","country_code":"NL","type":"company","lineage":["https://openalex.org/I109147379"]},{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"J.P. de Gyvez","raw_affiliation_strings":["Eindhovan University of Technology, Eindhoven, Netherlands","NXP Semiconductors, Eindhoven, Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Eindhovan University of Technology, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I83019370"]},{"raw_affiliation_string":"NXP Semiconductors, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I109147379"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.1527,"has_fulltext":true,"cited_by_count":9,"citation_normalized_percentile":{"value":0.81443668,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"17","issue":"10","first_page":"1383","last_page":"1391"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.8461712598800659},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.6976187825202942},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.6344879865646362},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.5608636736869812},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.5438147783279419},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.532407820224762},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5270072221755981},{"id":"https://openalex.org/keywords/stuck-at-fault","display_name":"Stuck-at fault","score":0.5026545524597168},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.49312373995780945},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.48623743653297424},{"id":"https://openalex.org/keywords/fault-detection-and-isolation","display_name":"Fault detection and isolation","score":0.46345824003219604},{"id":"https://openalex.org/keywords/automatic-test-equipment","display_name":"Automatic test equipment","score":0.4563404619693756},{"id":"https://openalex.org/keywords/test-method","display_name":"Test method","score":0.4373897612094879},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.43717318773269653},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4127534329891205},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.303973913192749},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.2935296595096588},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.27867069840431213},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.25645536184310913},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24236229062080383},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.23681429028511047},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15307673811912537},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12410441040992737},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.09447795152664185},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.09411883354187012}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.8461712598800659},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.6976187825202942},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.6344879865646362},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.5608636736869812},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.5438147783279419},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.532407820224762},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5270072221755981},{"id":"https://openalex.org/C13625343","wikidata":"https://www.wikidata.org/wiki/Q7627418","display_name":"Stuck-at fault","level":4,"score":0.5026545524597168},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.49312373995780945},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.48623743653297424},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.46345824003219604},{"id":"https://openalex.org/C141842801","wikidata":"https://www.wikidata.org/wiki/Q363815","display_name":"Automatic test equipment","level":3,"score":0.4563404619693756},{"id":"https://openalex.org/C132519959","wikidata":"https://www.wikidata.org/wiki/Q3077373","display_name":"Test method","level":2,"score":0.4373897612094879},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.43717318773269653},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4127534329891205},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.303973913192749},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2935296595096588},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.27867069840431213},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.25645536184310913},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24236229062080383},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.23681429028511047},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15307673811912537},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12410441040992737},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09447795152664185},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.09411883354187012},{"id":"https://openalex.org/C172707124","wikidata":"https://www.wikidata.org/wiki/Q423488","display_name":"Actuator","level":2,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":6,"locations":[{"id":"doi:10.1109/tvlsi.2008.2003517","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2003517","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:pure.tue.nl:openaire_cris_publications/572b4113-d072-4c5c-8fd9-4342e4f11dc1","is_oa":true,"landing_page_url":"https://research.tue.nl/en/publications/572b4113-d072-4c5c-8fd9-4342e4f11dc1","pdf_url":"https://pure.tue.nl/ws/files/3305960/Metis231262.pdf","source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Zjajo, A & Pineda de Gyvez, J 2009, 'Analog automatic test pattern generation for quasi-static structural test.', IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 17, pp. 1383-1391. https://doi.org/10.1109/TVLSI.2008.2003517","raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:657080","is_oa":false,"landing_page_url":"http://library.tue.nl/csp/dare/LinkToRepository.csp?recordnumber=657080","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISSN:1063-8210","raw_type":"Article / Letter to the editor"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.666.9516","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.666.9516","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://alexandria.tue.nl/openaccess/Metis231262.pdf","raw_type":"text"},{"id":"pmh:oai:library.tue.nl:657080","is_oa":false,"landing_page_url":"http://repository.tue.nl/657080","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISSN:1063-8210","raw_type":"Article / Letter to the editor"},{"id":"pmh:tue:oai:pure.tue.nl:publications/572b4113-d072-4c5c-8fd9-4342e4f11dc1","is_oa":true,"landing_page_url":"https://research.tue.nl/nl/publications/572b4113-d072-4c5c-8fd9-4342e4f11dc1","pdf_url":null,"source":{"id":"https://openalex.org/S4306401843","display_name":"Data Archiving and Networked Services (DANS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1322597698","host_organization_name":"Royal Netherlands Academy of Arts and Sciences","host_organization_lineage":["https://openalex.org/I1322597698"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(17), 1383 - 1391. Institute of Electrical and Electronics Engineers","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:pure.tue.nl:openaire_cris_publications/572b4113-d072-4c5c-8fd9-4342e4f11dc1","is_oa":true,"landing_page_url":"https://research.tue.nl/en/publications/572b4113-d072-4c5c-8fd9-4342e4f11dc1","pdf_url":"https://pure.tue.nl/ws/files/3305960/Metis231262.pdf","source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Zjajo, A & Pineda de Gyvez, J 2009, 'Analog automatic test pattern generation for quasi-static structural test.', IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 17, pp. 1383-1391. https://doi.org/10.1109/TVLSI.2008.2003517","raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2096686240.pdf","grobid_xml":"https://content.openalex.org/works/W2096686240.grobid-xml"},"referenced_works_count":24,"referenced_works":["https://openalex.org/W1538934584","https://openalex.org/W1546592019","https://openalex.org/W1556432061","https://openalex.org/W1693570377","https://openalex.org/W1964067494","https://openalex.org/W1990476418","https://openalex.org/W2028504835","https://openalex.org/W2079460691","https://openalex.org/W2096193492","https://openalex.org/W2106816366","https://openalex.org/W2114435646","https://openalex.org/W2121133433","https://openalex.org/W2121437951","https://openalex.org/W2133229660","https://openalex.org/W2155221776","https://openalex.org/W2156459628","https://openalex.org/W2178225970","https://openalex.org/W2798461040","https://openalex.org/W2993330478","https://openalex.org/W3153172827","https://openalex.org/W4244195727","https://openalex.org/W4251448448","https://openalex.org/W6674492458","https://openalex.org/W6683144395"],"related_works":["https://openalex.org/W4245311057","https://openalex.org/W311918050","https://openalex.org/W2543176856","https://openalex.org/W2165948443","https://openalex.org/W2550015578","https://openalex.org/W2377850316","https://openalex.org/W2146381271","https://openalex.org/W2061326683","https://openalex.org/W2989178840","https://openalex.org/W565729072"],"abstract_inverted_index":{"A":[0],"new":[1],"approach":[2],"for":[3,12,82],"structural,":[4],"fault-oriented":[5],"analog":[6],"test":[7,11,24,29,77],"generation":[8],"methodology":[9],"to":[10,39],"the":[13,23,41,45,62,71,76,83,87],"presence":[14],"of":[15,22,27,67,89],"manufacturing-related":[16],"defects":[17],"is":[18],"proposed.":[19],"The":[20,49],"output":[21],"generator":[25,78],"consists":[26],"optimized":[28],"stimuli,":[30],"fault":[31,64],"coverage":[32],"and":[33,53,93],"sampling":[34],"instants":[35],"that":[36],"are":[37,51],"sufficient":[38],"detect":[40],"failure":[42],"modes":[43],"in":[44],"circuit":[46,73,84,90],"under":[47],"test.":[48],"tests":[50],"generated":[52],"evaluated":[54],"on":[55,70],"a":[56],"multistep":[57],"ADC":[58],"taking":[59],"into":[60],"account":[61],"potential":[63],"masking":[65],"effects":[66],"process":[68],"spread":[69],"faulty":[72],"responses.":[74],"Similarly,":[75],"results":[79],"offer":[80],"indication":[81],"partitioning":[85],"within":[86],"framework":[88],"performance,":[91],"area":[92],"testability.":[94]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-28T07:46:37.118299","created_date":"2025-10-10T00:00:00"}
