{"id":"https://openalex.org/W2137587811","doi":"https://doi.org/10.1109/tvlsi.2008.2001298","title":"A Special-Purpose Architecture for Solving the Breakpoint Median Problem","display_name":"A Special-Purpose Architecture for Solving the Breakpoint Median Problem","publication_year":2008,"publication_date":"2008-11-25","ids":{"openalex":"https://openalex.org/W2137587811","doi":"https://doi.org/10.1109/tvlsi.2008.2001298","mag":"2137587811"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2008.2001298","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2001298","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5001266986","display_name":"Jason D. Bakos","orcid":"https://orcid.org/0000-0002-0821-6258"},"institutions":[{"id":"https://openalex.org/I155781252","display_name":"University of South Carolina","ror":"https://ror.org/02b6qw903","country_code":"US","type":"education","lineage":["https://openalex.org/I155781252"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jason D. Bakos","raw_affiliation_strings":["Department of Computer Science and Engineering, University of South Carolina, Columbia, SC, USA","Dept. of Comput. Sci. & Eng., Univ. of South Carolina, Columbia, SC"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, University of South Carolina, Columbia, SC, USA","institution_ids":["https://openalex.org/I155781252"]},{"raw_affiliation_string":"Dept. of Comput. Sci. & Eng., Univ. of South Carolina, Columbia, SC","institution_ids":["https://openalex.org/I155781252"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076415234","display_name":"Panormitis E. Elenis","orcid":null},"institutions":[{"id":"https://openalex.org/I155781252","display_name":"University of South Carolina","ror":"https://ror.org/02b6qw903","country_code":"US","type":"education","lineage":["https://openalex.org/I155781252"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Panormitis E. Elenis","raw_affiliation_strings":["Department of Computer Science and Engineering, University of South Carolina, Columbia, SC, USA","Dept. of Comput. Sci. & Eng., Univ. of South Carolina, Columbia, SC"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, University of South Carolina, Columbia, SC, USA","institution_ids":["https://openalex.org/I155781252"]},{"raw_affiliation_string":"Dept. of Comput. Sci. & Eng., Univ. of South Carolina, Columbia, SC","institution_ids":["https://openalex.org/I155781252"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.1685,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.8141323,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"16","issue":"12","first_page":"1666","last_page":"1676"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T13664","display_name":"Genome Rearrangement Algorithms","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1311","display_name":"Genetics"},"field":{"id":"https://openalex.org/fields/13","display_name":"Biochemistry, Genetics and Molecular Biology"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},"topics":[{"id":"https://openalex.org/T13664","display_name":"Genome Rearrangement Algorithms","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1311","display_name":"Genetics"},"field":{"id":"https://openalex.org/fields/13","display_name":"Biochemistry, Genetics and Molecular Biology"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T10015","display_name":"Genomics and Phylogenetic Studies","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1312","display_name":"Molecular Biology"},"field":{"id":"https://openalex.org/fields/13","display_name":"Biochemistry, Genetics and Molecular Biology"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.9120789766311646},{"id":"https://openalex.org/keywords/coprocessor","display_name":"Coprocessor","score":0.8452043533325195},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7249727249145508},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6904489994049072},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6789727210998535},{"id":"https://openalex.org/keywords/breakpoint","display_name":"Breakpoint","score":0.5906203389167786},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.5745912790298462},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.4782342314720154},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4700298011302948},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.371730238199234},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3344155550003052},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.20462548732757568}],"concepts":[{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.9120789766311646},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.8452043533325195},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7249727249145508},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6904489994049072},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6789727210998535},{"id":"https://openalex.org/C206936463","wikidata":"https://www.wikidata.org/wiki/Q634179","display_name":"Breakpoint","level":4,"score":0.5906203389167786},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.5745912790298462},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.4782342314720154},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4700298011302948},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.371730238199234},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3344155550003052},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.20462548732757568},{"id":"https://openalex.org/C138626823","wikidata":"https://www.wikidata.org/wiki/Q916504","display_name":"Chromosomal translocation","level":3,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tvlsi.2008.2001298","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2001298","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:scholarcommons.sc.edu:csce_facpub-1081","is_oa":false,"landing_page_url":"https://scholarcommons.sc.edu/csce_facpub/82","pdf_url":null,"source":{"id":"https://openalex.org/S4306401386","display_name":"Scholar Commons (University of South Carolina)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I155781252","host_organization_name":"University of South Carolina","host_organization_lineage":["https://openalex.org/I155781252"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Faculty Publications","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.162.876","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.162.876","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cse.sc.edu/~jbakos/papers/vlsi2008_paper.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.41999998688697815,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":35,"referenced_works":["https://openalex.org/W152315924","https://openalex.org/W1566539040","https://openalex.org/W1567890695","https://openalex.org/W1572531572","https://openalex.org/W1584190736","https://openalex.org/W1592788845","https://openalex.org/W1975922463","https://openalex.org/W2004902010","https://openalex.org/W2018092436","https://openalex.org/W2022920802","https://openalex.org/W2026452889","https://openalex.org/W2041797002","https://openalex.org/W2043198910","https://openalex.org/W2048659620","https://openalex.org/W2097706568","https://openalex.org/W2097821322","https://openalex.org/W2100665964","https://openalex.org/W2117766032","https://openalex.org/W2124150072","https://openalex.org/W2124862004","https://openalex.org/W2131853686","https://openalex.org/W2133090982","https://openalex.org/W2151333238","https://openalex.org/W2157183438","https://openalex.org/W2157312689","https://openalex.org/W2166760518","https://openalex.org/W2168698047","https://openalex.org/W2542477824","https://openalex.org/W2750757353","https://openalex.org/W3145289361","https://openalex.org/W6633852976","https://openalex.org/W6634977875","https://openalex.org/W6675268794","https://openalex.org/W6680058235","https://openalex.org/W6682573666"],"related_works":["https://openalex.org/W2058965144","https://openalex.org/W2164382479","https://openalex.org/W2146343568","https://openalex.org/W2291943064","https://openalex.org/W2209727271","https://openalex.org/W2027176516","https://openalex.org/W2057084000","https://openalex.org/W2532502681","https://openalex.org/W4394999","https://openalex.org/W2106011773"],"abstract_inverted_index":{"In":[0],"this":[1,74],"paper,":[2],"we":[3,63],"describe":[4],"the":[5,29,53,59,92,95],"design":[6,16],"for":[7,10,84],"a":[8,18,35,45,65,81],"co-processor":[9],"whole-genome":[11],"phylogenetic":[12,87],"reconstruction.":[13],"Our":[14],"current":[15],"performs":[17],"parallelized":[19],"breakpoint":[20,42],"median":[21,43],"computation,":[22],"which":[23],"is":[24,55,80],"an":[25],"expensive":[26,86],"component":[27],"of":[28,48,69,91],"overall":[30],"application.":[31],"When":[32,52],"implemented":[33],"on":[34,100],"field-programmable":[36],"gate":[37],"array":[38],"(FPGA),":[39],"our":[40],"hardware":[41],"achieves":[44],"maximum":[46,66],"speedup":[47,68],"1005times":[49],"over":[50],"software.":[51],"coprocessor":[54],"used":[56],"to":[57],"accelerate":[58],"entire":[60],"reconstruction":[61],"procedure,":[62],"achieve":[64],"application":[67],"417times.":[70],"The":[71],"results":[72],"in":[73,89],"paper":[75],"suggest":[76],"that":[77,94],"FPGA-based":[78],"acceleration":[79],"promising":[82],"approach":[83],"computationally":[85],"problems,":[88],"spite":[90],"fact":[93],"involved":[96],"algorithms":[97],"are":[98],"based":[99],"complex,":[101],"control-dependent":[102],"combinatorial":[103],"optimization.":[104]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
