{"id":"https://openalex.org/W2106106074","doi":"https://doi.org/10.1109/tvlsi.2008.2001238","title":"Wire Topology Optimization for Low Power CMOS","display_name":"Wire Topology Optimization for Low Power CMOS","publication_year":2008,"publication_date":"2008-12-17","ids":{"openalex":"https://openalex.org/W2106106074","doi":"https://doi.org/10.1109/tvlsi.2008.2001238","mag":"2106106074"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2008.2001238","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2001238","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079692388","display_name":"Paul Zuber","orcid":null},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"P. Zuber","raw_affiliation_strings":["Lehrstuhl f\u00fcr Integrierte Systeme Institute of Integrated Systems, Technische Universit\u00e4t M\u00fcnchen, Munich, Germany","Technol. Aware Design, Interuniversity Microelectron. Center, Lowen"],"affiliations":[{"raw_affiliation_string":"Lehrstuhl f\u00fcr Integrierte Systeme Institute of Integrated Systems, Technische Universit\u00e4t M\u00fcnchen, Munich, Germany","institution_ids":["https://openalex.org/I62916508"]},{"raw_affiliation_string":"Technol. Aware Design, Interuniversity Microelectron. Center, Lowen","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074609252","display_name":"O. Bahlous","orcid":null},"institutions":[{"id":"https://openalex.org/I137594350","display_name":"Infineon Technologies (Germany)","ror":"https://ror.org/005kw6t15","country_code":"DE","type":"company","lineage":["https://openalex.org/I137594350"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"O. Bahlous","raw_affiliation_strings":["AIM MC ATM MD, Infineon Technologies, Neubiberg, Germany","AIM MC ATM MD, Infineon Technologies AG, Neubiberg, Germany#TAB#"],"affiliations":[{"raw_affiliation_string":"AIM MC ATM MD, Infineon Technologies, Neubiberg, Germany","institution_ids":["https://openalex.org/I137594350"]},{"raw_affiliation_string":"AIM MC ATM MD, Infineon Technologies AG, Neubiberg, Germany#TAB#","institution_ids":["https://openalex.org/I137594350"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082239516","display_name":"Thomas Ilnseher","orcid":null},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"T. Ilnseher","raw_affiliation_strings":["Mikroelektronischer Systeme Microelectronic Systems Design Research Group, Universit\u00e4t Kaiserslautern, Kaiserslautern, Germany","Lehrstuhl Entwurf Mikroelektronischer Systeme, Universit\u00e4t Kaiserslautern, Kaiserslautern, Germany#TAB#"],"affiliations":[{"raw_affiliation_string":"Mikroelektronischer Systeme Microelectronic Systems Design Research Group, Universit\u00e4t Kaiserslautern, Kaiserslautern, Germany","institution_ids":["https://openalex.org/I153267046"]},{"raw_affiliation_string":"Lehrstuhl Entwurf Mikroelektronischer Systeme, Universit\u00e4t Kaiserslautern, Kaiserslautern, Germany#TAB#","institution_ids":["https://openalex.org/I153267046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035767523","display_name":"Michael Ritter","orcid":"https://orcid.org/0000-0002-4767-9618"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"M. Ritter","raw_affiliation_strings":["Zentrum Mathematick M9, Technische Universit\u00e4t M\u00fcnchen, Garching, Germany","Zentrum Mathematik, Technische Universit\u00e4 M\u00fcnchen, Garching bei M\u00fcnchen, Germany#TAB#"],"affiliations":[{"raw_affiliation_string":"Zentrum Mathematick M9, Technische Universit\u00e4t M\u00fcnchen, Garching, Germany","institution_ids":["https://openalex.org/I62916508"]},{"raw_affiliation_string":"Zentrum Mathematik, Technische Universit\u00e4 M\u00fcnchen, Garching bei M\u00fcnchen, Germany#TAB#","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005732789","display_name":"Walter Stechele","orcid":"https://orcid.org/0000-0002-7455-8483"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"W. Stechele","raw_affiliation_strings":["Lehrstuhl f\u00fcr Integrierte Systeme Institute of Integrated Systems, Technische Universit\u00e4t M\u00fcnchen, Munich, Germany","Lehrstuhl f\u00fc Integrierte Systeme, Technische Universit\u00e4 M\u00fcnchen, M\u00fcnchen, Germany#TAB#"],"affiliations":[{"raw_affiliation_string":"Lehrstuhl f\u00fcr Integrierte Systeme Institute of Integrated Systems, Technische Universit\u00e4t M\u00fcnchen, Munich, Germany","institution_ids":["https://openalex.org/I62916508"]},{"raw_affiliation_string":"Lehrstuhl f\u00fc Integrierte Systeme, Technische Universit\u00e4 M\u00fcnchen, M\u00fcnchen, Germany#TAB#","institution_ids":["https://openalex.org/I62916508"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5079692388"],"corresponding_institution_ids":["https://openalex.org/I62916508"],"apc_list":null,"apc_paid":null,"fwci":1.6647,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.84651843,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"17","issue":"1","first_page":"1","last_page":"11"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6865081787109375},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6813508868217468},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5444614887237549},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5395142436027527},{"id":"https://openalex.org/keywords/limit","display_name":"Limit (mathematics)","score":0.5363003611564636},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.530036449432373},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5293845534324646},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4766536355018616},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.46245670318603516},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4595971703529358},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.45469748973846436},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.45147505402565},{"id":"https://openalex.org/keywords/power-optimization","display_name":"Power optimization","score":0.4440886676311493},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.42966610193252563},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.42779725790023804},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4268903434276581},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.413309246301651},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3158237636089325},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.29637080430984497},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2932708263397217},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.15301692485809326},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13782143592834473},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1008419394493103}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6865081787109375},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6813508868217468},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5444614887237549},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5395142436027527},{"id":"https://openalex.org/C151201525","wikidata":"https://www.wikidata.org/wiki/Q177239","display_name":"Limit (mathematics)","level":2,"score":0.5363003611564636},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.530036449432373},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5293845534324646},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4766536355018616},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.46245670318603516},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4595971703529358},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.45469748973846436},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.45147505402565},{"id":"https://openalex.org/C168292644","wikidata":"https://www.wikidata.org/wiki/Q10860336","display_name":"Power optimization","level":4,"score":0.4440886676311493},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.42966610193252563},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.42779725790023804},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4268903434276581},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.413309246301651},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3158237636089325},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.29637080430984497},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2932708263397217},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.15301692485809326},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13782143592834473},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1008419394493103},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2008.2001238","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2001238","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6700000166893005,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W114336036","https://openalex.org/W1510557987","https://openalex.org/W1538996567","https://openalex.org/W1593675831","https://openalex.org/W1999108518","https://openalex.org/W2068587771","https://openalex.org/W2084928670","https://openalex.org/W2110134128","https://openalex.org/W2120527478","https://openalex.org/W2121235640","https://openalex.org/W2124618076","https://openalex.org/W2138334578","https://openalex.org/W2159201497","https://openalex.org/W2160347664","https://openalex.org/W2167848093","https://openalex.org/W2739148627","https://openalex.org/W3151993598","https://openalex.org/W4242730096","https://openalex.org/W6671798625","https://openalex.org/W6683700830"],"related_works":["https://openalex.org/W4244547561","https://openalex.org/W2388040150","https://openalex.org/W4253195573","https://openalex.org/W1519976071","https://openalex.org/W2020934033","https://openalex.org/W63276784","https://openalex.org/W4230718388","https://openalex.org/W3149244010","https://openalex.org/W2047284788","https://openalex.org/W2009503188"],"abstract_inverted_index":{"An":[0],"increasing":[1],"fraction":[2],"of":[3,76],"dynamic":[4],"power":[5,23,74],"consumption":[6],"can":[7],"be":[8],"attributed":[9],"to":[10,78],"switched":[11],"interconnect":[12],"capacitances.":[13],"Non-uniform":[14],"wire":[15],"spacing":[16,41],"depending":[17],"on":[18,39],"activity":[19],"had":[20],"shown":[21],"promising":[22],"reductions":[24,75],"for":[25,44,80],"on-chip":[26],"buses.":[27],"In":[28],"this":[29],"paper,":[30],"a":[31],"new":[32],"and":[33,66,108],"fast":[34],"routing":[35,57],"optimization":[36],"methodology":[37,62],"based":[38],"non-uniform":[40],"is":[42,50,58,104,112],"proposed":[43,61],"entire":[45],"circuits.":[46],"No":[47],"area":[48,86],"investment":[49],"required,":[51],"since":[52],"whitespace":[53],"remaining":[54],"after":[55],"detailed":[56],"exploited.":[59],"The":[60],"has":[63],"been":[64],"implemented":[65],"tapped":[67],"into":[68,101],"an":[69],"industry-proven":[70],"design":[71],"flow.":[72],"Wire":[73],"up":[77],"9.55%":[79],"modern":[81],"multiprocessor":[82],"benchmarks":[83],"with":[84],"tight":[85],"constraints":[87],"are":[88],"demonstrated,":[89],"twice":[90],"as":[91,93],"much":[92],"approaches":[94],"that":[95],"do":[96],"not":[97,105],"take":[98],"switching":[99],"activities":[100],"account.":[102],"Timing":[103],"adversely":[106],"affected,":[107],"the":[109],"yield":[110],"limit":[111],"slightly":[113],"improved.":[114]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
