{"id":"https://openalex.org/W2148701953","doi":"https://doi.org/10.1109/tvlsi.2008.2001237","title":"GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering","display_name":"GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering","publication_year":2008,"publication_date":"2008-10-22","ids":{"openalex":"https://openalex.org/W2148701953","doi":"https://doi.org/10.1109/tvlsi.2008.2001237","mag":"2148701953"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2008.2001237","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2001237","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074883642","display_name":"Julien Lamoureux","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Julien Lamoureux","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071113717","display_name":"Guy Lemieux","orcid":"https://orcid.org/0000-0002-7924-8695"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Guy G. F. Lemieux","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013246362","display_name":"Steven J. E. Wilton","orcid":"https://orcid.org/0000-0002-1241-6690"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Steven J. E. Wilton","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":null,"apc_paid":null,"fwci":5.7099,"has_fulltext":false,"cited_by_count":45,"citation_normalized_percentile":{"value":0.96156852,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"16","issue":"11","first_page":"1521","last_page":"1534"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/glitch","display_name":"Glitch","score":0.8575896620750427},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.7878121137619019},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7830176949501038},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6421064138412476},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6240440607070923},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.5450451970100403},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5403177738189697},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.5349942445755005},{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.5149258375167847},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5096828937530518},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.4794144332408905},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4610530436038971},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.45886608958244324},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.41765880584716797},{"id":"https://openalex.org/keywords/macrocell-array","display_name":"Macrocell array","score":0.4148525595664978},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.39810821413993835},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36215656995773315},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.3305121660232544},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.25509172677993774},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23887550830841064},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.2045656144618988},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.13351139426231384},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.12411552667617798}],"concepts":[{"id":"https://openalex.org/C191287063","wikidata":"https://www.wikidata.org/wiki/Q543281","display_name":"Glitch","level":3,"score":0.8575896620750427},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.7878121137619019},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7830176949501038},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6421064138412476},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6240440607070923},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.5450451970100403},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5403177738189697},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.5349942445755005},{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.5149258375167847},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5096828937530518},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.4794144332408905},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4610530436038971},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.45886608958244324},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.41765880584716797},{"id":"https://openalex.org/C142278197","wikidata":"https://www.wikidata.org/wiki/Q4284934","display_name":"Macrocell array","level":5,"score":0.4148525595664978},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.39810821413993835},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36215656995773315},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.3305121660232544},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.25509172677993774},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23887550830841064},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.2045656144618988},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.13351139426231384},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.12411552667617798},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/tvlsi.2008.2001237","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2001237","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.122.77","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.122.77","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.ubc.ca/~julienl/papers/pdf/tvlsi07.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.380.3908","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.380.3908","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.ubc.ca/~lemieux/publications/lamoureux-tvlsi2008.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.486.9305","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.486.9305","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.ubc.ca/~julienl/papers/pdf/tvlsi08.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6600000262260437,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1557877906","https://openalex.org/W1992431113","https://openalex.org/W2001824086","https://openalex.org/W2007856151","https://openalex.org/W2017650358","https://openalex.org/W2033685698","https://openalex.org/W2049204312","https://openalex.org/W2077892593","https://openalex.org/W2095558812","https://openalex.org/W2098762322","https://openalex.org/W2111485030","https://openalex.org/W2128264388","https://openalex.org/W2132225593","https://openalex.org/W2137769675","https://openalex.org/W2140615181","https://openalex.org/W2141752451","https://openalex.org/W2146589686","https://openalex.org/W2155776339","https://openalex.org/W2158151684","https://openalex.org/W2163580033","https://openalex.org/W3151556488","https://openalex.org/W4246961877","https://openalex.org/W4248668797","https://openalex.org/W6633444049","https://openalex.org/W6679240198","https://openalex.org/W6681891284"],"related_works":["https://openalex.org/W3117015220","https://openalex.org/W1528933814","https://openalex.org/W2466591189","https://openalex.org/W3013792460","https://openalex.org/W2014165129","https://openalex.org/W2764789987","https://openalex.org/W2038293309","https://openalex.org/W2054740893","https://openalex.org/W2085192548","https://openalex.org/W2100931776"],"abstract_inverted_index":{"This":[0,22],"paper":[1],"describes":[2],"GlitchLess,":[3],"a":[4,39],"circuit-level":[5],"technique":[6,133],"for":[7],"reducing":[8],"power":[9,104],"in":[10],"field-programmable":[11],"gate":[12],"arrays":[13],"(FPGAs)":[14],"by":[15,25,84,105,115,120],"eliminating":[16],"unnecessary":[17],"logic":[18,32,86],"transitions":[19],"called":[20],"glitches.":[21],"is":[23,127],"done":[24],"adding":[26],"programmable":[27],"delay":[28,47,73,119],"elements":[29,48,74],"to":[30,51,139],"the":[31,35,53,57,72,92,98,111,131,140],"blocks":[33],"of":[34,56,59,97],"FPGA.":[36],"After":[37],"routing":[38,141],"circuit":[40],"and":[41,117],"performing":[42],"static":[43],"timing":[44],"analysis,":[45],"these":[46],"are":[49],"programmed":[50],"align":[52],"arrival":[54],"times":[55],"inputs":[58],"each":[60],"lookup":[61],"table":[62],"(LUT),":[63],"thereby":[64],"preventing":[65],"new":[66],"glitches":[67,82],"from":[68],"being":[69],"generated.":[70],"Moreover,":[71],"also":[75],"behave":[76],"as":[77],"filters":[78],"that":[79],"eliminate":[80],"other":[81],"generated":[83],"upstream":[85],"or":[87,136,143],"off-chip":[88],"circuitry.":[89],"On":[90],"average,":[91],"proposed":[93,132],"implementation":[94],"eliminates":[95],"87%":[96],"glitching,":[99],"which":[100],"reduces":[101],"overall":[102,112],"FPGA":[103,113],"17%.":[106],"The":[107],"added":[108],"circuitry":[109],"increases":[110],"area":[114],"6%":[116],"critical-path":[118],"less":[121],"than":[122],"1%.":[123],"Furthermore,":[124],"since":[125],"it":[126],"applied":[128],"after":[129],"routing,":[130],"requires":[134],"little":[135],"no":[137],"modifications":[138],"architecture":[142],"computer-aided":[144],"design":[145],"(CAD)":[146],"flow.":[147]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":5},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
