{"id":"https://openalex.org/W2110852658","doi":"https://doi.org/10.1109/tvlsi.2008.2001060","title":"A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies","display_name":"A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies","publication_year":2008,"publication_date":"2008-10-22","ids":{"openalex":"https://openalex.org/W2110852658","doi":"https://doi.org/10.1109/tvlsi.2008.2001060","mag":"2110852658"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2008.2001060","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2001060","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102143883","display_name":"Sheng\u2010Chih Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sheng-Chih Lin","raw_affiliation_strings":["Intel Corporation, Chandler, AZ, USA","Intel Corporation, Chandler, AZ#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Chandler, AZ, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Chandler, AZ#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5075851236","display_name":"Kaustav Banerjee","orcid":"https://orcid.org/0000-0001-5344-0921"},"institutions":[{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kaustav Banerjee","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA, USA","Dept. of Electrical and Computer Engineering, Univ. of California, Santa Barbara, CA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA, USA","institution_ids":["https://openalex.org/I154570441"]},{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Univ. of California, Santa Barbara, CA#TAB#","institution_ids":["https://openalex.org/I154570441"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3359,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.65287678,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"16","issue":"11","first_page":"1488","last_page":"1498"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7783665657043457},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6484513282775879},{"id":"https://openalex.org/keywords/performance-metric","display_name":"Performance metric","score":0.609136164188385},{"id":"https://openalex.org/keywords/metric","display_name":"Metric (unit)","score":0.5881500840187073},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5826659202575684},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5267607569694519},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.5088379979133606},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.48593416810035706},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.47928565740585327},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4556189179420471},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4430384039878845},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3228367567062378},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.24694812297821045},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07698330283164978}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7783665657043457},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6484513282775879},{"id":"https://openalex.org/C2780898871","wikidata":"https://www.wikidata.org/wiki/Q860554","display_name":"Performance metric","level":2,"score":0.609136164188385},{"id":"https://openalex.org/C176217482","wikidata":"https://www.wikidata.org/wiki/Q860554","display_name":"Metric (unit)","level":2,"score":0.5881500840187073},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5826659202575684},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5267607569694519},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.5088379979133606},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.48593416810035706},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.47928565740585327},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4556189179420471},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4430384039878845},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3228367567062378},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.24694812297821045},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07698330283164978},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C187736073","wikidata":"https://www.wikidata.org/wiki/Q2920921","display_name":"Management","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2008.2001060","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2001060","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":47,"referenced_works":["https://openalex.org/W185357548","https://openalex.org/W1541741077","https://openalex.org/W1556480701","https://openalex.org/W1575022128","https://openalex.org/W1661368752","https://openalex.org/W1984588379","https://openalex.org/W2003652851","https://openalex.org/W2025516544","https://openalex.org/W2037921569","https://openalex.org/W2069270260","https://openalex.org/W2075059680","https://openalex.org/W2078835261","https://openalex.org/W2087645421","https://openalex.org/W2103078379","https://openalex.org/W2103684670","https://openalex.org/W2108519747","https://openalex.org/W2111013026","https://openalex.org/W2115052657","https://openalex.org/W2117648153","https://openalex.org/W2123405452","https://openalex.org/W2123793459","https://openalex.org/W2124827086","https://openalex.org/W2127223786","https://openalex.org/W2128276907","https://openalex.org/W2134067926","https://openalex.org/W2138093253","https://openalex.org/W2144196852","https://openalex.org/W2149009819","https://openalex.org/W2153677786","https://openalex.org/W2159448561","https://openalex.org/W2159974434","https://openalex.org/W2160010046","https://openalex.org/W2162211138","https://openalex.org/W2168843308","https://openalex.org/W2169065640","https://openalex.org/W2533651815","https://openalex.org/W2543182634","https://openalex.org/W3103339143","https://openalex.org/W3149772516","https://openalex.org/W3203992401","https://openalex.org/W4241665042","https://openalex.org/W4243899494","https://openalex.org/W6632441499","https://openalex.org/W6667807231","https://openalex.org/W6677287792","https://openalex.org/W6678610342","https://openalex.org/W6679358392"],"related_works":["https://openalex.org/W2081032080","https://openalex.org/W2134733504","https://openalex.org/W2144460576","https://openalex.org/W2765822612","https://openalex.org/W3094423394","https://openalex.org/W1553422968","https://openalex.org/W2046159858","https://openalex.org/W2007385019","https://openalex.org/W2338273177","https://openalex.org/W2168458994"],"abstract_inverted_index":{"As":[0],"CMOS":[1,149],"technology":[2,150],"scales":[3],"deeper":[4],"into":[5],"the":[6,33,46,156],"nanometer":[7,67,92],"regime,":[8],"factors":[9],"such":[10],"as":[11,18,80,82],"leakage":[12],"power":[13,63],"and":[14,64,89,107,112,130,143,152],"chip":[15],"temperature":[16,109,142],"emerge":[17],"critically":[19],"important":[20,35],"concerns":[21],"for":[22,45,60,91],"high-performance":[23],"VLSI":[24],"design.":[25],"Consequently,":[26],"enhancing":[27],"processing":[28],"performance":[29,65,90],"is":[30,117],"no":[31],"longer":[32],"most":[34],"factor":[36],"that":[37],"dominates":[38],"future":[39],"circuit":[40],"design":[41,57,94,101],"considerations.":[42],"This":[43],"paper,":[44],"first":[47],"time,":[48],"proposes":[49],"a":[50,55,99,121],"systematic":[51],"methodology":[52,76,116,158],"to":[53,71,119],"determine":[54],"generalized":[56],"optimization":[58,102,124],"metric":[59,103,125],"simultaneously":[61],"trading-off":[62],"in":[66],"scale":[68,93],"integrated":[69],"circuits":[70],"achieve":[72],"design-specific":[73],"targets.":[74],"The":[75,114],"incorporates":[77],"interconnect":[78],"effects":[79],"well":[81],"electrothermal":[83],"couplings":[84],"between":[85],"substrate":[86],"temperature,":[87],"power,":[88,105],"optimization.":[95],"Implications":[96],"of":[97,134,148],"choosing":[98],"specific":[100],"on":[104,155],"performance,":[106],"operating":[108,141],"are":[110,159],"illustrated":[111],"discussed.":[113,160],"proposed":[115,157],"shown":[118],"provide":[120],"more":[122],"meaningful":[123],"(for":[126],"power-performance":[127],"tradeoff":[128],"analysis)":[129],"basis,":[131],"with":[132],"considerations":[133],"chip-level":[135],"thermal":[136],"management":[137],"including":[138],"maximum":[139],"allowable":[140],"packaging/cooling":[144],"solutions.":[145],"Furthermore,":[146],"implications":[147],"scaling":[151],"parameter":[153],"variations":[154]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}