{"id":"https://openalex.org/W2113480331","doi":"https://doi.org/10.1109/tvlsi.2008.2000821","title":"Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis","display_name":"Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis","publication_year":2008,"publication_date":"2008-08-19","ids":{"openalex":"https://openalex.org/W2113480331","doi":"https://doi.org/10.1109/tvlsi.2008.2000821","mag":"2113480331"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2008.2000821","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2000821","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079950326","display_name":"Bertrand Le Gal","orcid":"https://orcid.org/0000-0003-2269-8756"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I15057530","display_name":"Universit\u00e9 de Bordeaux","ror":"https://ror.org/057qpr032","country_code":"FR","type":"education","lineage":["https://openalex.org/I15057530"]},{"id":"https://openalex.org/I4210160189","display_name":"Institut Polytechnique de Bordeaux","ror":"https://ror.org/054qv7y42","country_code":"FR","type":"education","lineage":["https://openalex.org/I4210160189"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Bertrand Le Gal","raw_affiliation_strings":["IMS Laboratory UMR-CNRS 5218, ENSEIRB Computer and Electronic Engineering School, University of Bordeaux 1, Talence, France","IMS Lab., Bordeaux 1 Univ., Talence"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IMS Laboratory UMR-CNRS 5218, ENSEIRB Computer and Electronic Engineering School, University of Bordeaux 1, Talence, France","institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I15057530","https://openalex.org/I4210160189"]},{"raw_affiliation_string":"IMS Lab., Bordeaux 1 Univ., Talence","institution_ids":["https://openalex.org/I15057530","https://openalex.org/I4210160189"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070765151","display_name":"Emmanuel Casseau","orcid":"https://orcid.org/0000-0001-7216-749X"},"institutions":[{"id":"https://openalex.org/I2802519937","display_name":"Institut de Recherche en Informatique et Syst\u00e8mes Al\u00e9atoires","ror":"https://ror.org/00myn0z94","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I205703379","https://openalex.org/I2802204017","https://openalex.org/I2802519937","https://openalex.org/I28221208","https://openalex.org/I4210127572","https://openalex.org/I4210159245","https://openalex.org/I56067802"]},{"id":"https://openalex.org/I56067802","display_name":"Universit\u00e9 de Rennes","ror":"https://ror.org/015m7wh34","country_code":"FR","type":"education","lineage":["https://openalex.org/I56067802"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Emmanuel Casseau","raw_affiliation_strings":["CAIRN Team, IRISA Laboratory, ENSSAT Engineering School, Universite de Rennes 1, Lannion, France","CAIRN Team, IRISA Lab., ENSSAT Engineering School, Universit de Rennes 1, Lannion Cedex, France#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CAIRN Team, IRISA Laboratory, ENSSAT Engineering School, Universite de Rennes 1, Lannion, France","institution_ids":["https://openalex.org/I2802519937","https://openalex.org/I56067802"]},{"raw_affiliation_string":"CAIRN Team, IRISA Lab., ENSSAT Engineering School, Universit de Rennes 1, Lannion Cedex, France#TAB#","institution_ids":["https://openalex.org/I2802519937","https://openalex.org/I56067802"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051831310","display_name":"Sylvain Huet","orcid":"https://orcid.org/0000-0002-2989-3610"},"institutions":[{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I4210124956","display_name":"GIPSA-Lab","ror":"https://ror.org/02wrme198","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I4210124956","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Sylvain Huet","raw_affiliation_strings":["GIPSA-Laboratory, CNRS/INPG, Grenoble, France","GIPSA-Lab., CNRS, INPG, Grenoble, Grenoble Cedex, France#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"GIPSA-Laboratory, CNRS/INPG, Grenoble, France","institution_ids":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I4210124956"]},{"raw_affiliation_string":"GIPSA-Lab., CNRS, INPG, Grenoble, Grenoble Cedex, France#TAB#","institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I4210124956"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.6917,"has_fulltext":false,"cited_by_count":28,"citation_normalized_percentile":{"value":0.94046111,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"16","issue":"11","first_page":"1454","last_page":"1464"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.9262375831604004},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8553073406219482},{"id":"https://openalex.org/keywords/interfacing","display_name":"Interfacing","score":0.7074060440063477},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.5540317296981812},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.5364689230918884},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.517264187335968},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.49173906445503235},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.48617857694625854},{"id":"https://openalex.org/keywords/computing-with-memory","display_name":"Computing with Memory","score":0.46482327580451965},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4522098898887634},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.4404413104057312},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43945321440696716},{"id":"https://openalex.org/keywords/physical-address","display_name":"Physical address","score":0.43772703409194946},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.4324486255645752},{"id":"https://openalex.org/keywords/locality","display_name":"Locality","score":0.42657047510147095},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.422419011592865},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.40673309564590454},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.2523966431617737}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.9262375831604004},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8553073406219482},{"id":"https://openalex.org/C2776303644","wikidata":"https://www.wikidata.org/wiki/Q1020499","display_name":"Interfacing","level":2,"score":0.7074060440063477},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.5540317296981812},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.5364689230918884},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.517264187335968},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.49173906445503235},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.48617857694625854},{"id":"https://openalex.org/C152890283","wikidata":"https://www.wikidata.org/wiki/Q4129922","display_name":"Computing with Memory","level":5,"score":0.46482327580451965},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4522098898887634},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.4404413104057312},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43945321440696716},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.43772703409194946},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.4324486255645752},{"id":"https://openalex.org/C2779808786","wikidata":"https://www.wikidata.org/wiki/Q6664603","display_name":"Locality","level":2,"score":0.42657047510147095},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.422419011592865},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.40673309564590454},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.2523966431617737},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2008.2000821","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2000821","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:HAL:hal-00361870v1","is_oa":false,"landing_page_url":"https://hal.science/hal-00361870","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008, 16 (11), pp.1454-1464. &#x27E8;10.1109/TVLSI.2008.2000821&#x27E9;","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8700000047683716,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":51,"referenced_works":["https://openalex.org/W76152174","https://openalex.org/W236129104","https://openalex.org/W1490410396","https://openalex.org/W1566245157","https://openalex.org/W1567363020","https://openalex.org/W1590838657","https://openalex.org/W1593855808","https://openalex.org/W1990319215","https://openalex.org/W2031931305","https://openalex.org/W2038183992","https://openalex.org/W2043487772","https://openalex.org/W2087182434","https://openalex.org/W2090269583","https://openalex.org/W2091341414","https://openalex.org/W2103581911","https://openalex.org/W2108731475","https://openalex.org/W2109458549","https://openalex.org/W2109876904","https://openalex.org/W2110113956","https://openalex.org/W2111098157","https://openalex.org/W2112033081","https://openalex.org/W2113806166","https://openalex.org/W2115443376","https://openalex.org/W2117894736","https://openalex.org/W2120961842","https://openalex.org/W2126251399","https://openalex.org/W2128286046","https://openalex.org/W2128990057","https://openalex.org/W2130186880","https://openalex.org/W2140763472","https://openalex.org/W2141109916","https://openalex.org/W2145735609","https://openalex.org/W2146206484","https://openalex.org/W2148210292","https://openalex.org/W2152556892","https://openalex.org/W2156141410","https://openalex.org/W2161800984","https://openalex.org/W2165072326","https://openalex.org/W2493328864","https://openalex.org/W2777240051","https://openalex.org/W4230232370","https://openalex.org/W4230514636","https://openalex.org/W4231429702","https://openalex.org/W4240639279","https://openalex.org/W4244630320","https://openalex.org/W4245877671","https://openalex.org/W4248632208","https://openalex.org/W4253032652","https://openalex.org/W4253564390","https://openalex.org/W6609110956","https://openalex.org/W6747075218"],"related_works":["https://openalex.org/W2057195881","https://openalex.org/W2168550483","https://openalex.org/W2041174925","https://openalex.org/W3025845664","https://openalex.org/W1970751325","https://openalex.org/W4233816696","https://openalex.org/W3180803030","https://openalex.org/W2782503170","https://openalex.org/W2047684617","https://openalex.org/W2275997533"],"abstract_inverted_index":{"Multimedia":[0],"applications":[1],"such":[2],"as":[3,72,74,101,103],"video":[4],"and":[5,29,64,107,114],"image":[6],"processing":[7,22],"are":[8,27],"often":[9],"characterized":[10],"by":[11],"a":[12,60],"huge":[13],"number":[14],"of":[15,83],"data":[16,108],"accesses.":[17],"In":[18,31,44],"many":[19],"digital":[20],"signal":[21],"applications,":[23],"array":[24],"access":[25,39],"patterns":[26,71],"regular":[28],"periodic.":[30],"these":[32],"cases,":[33],"optimized":[34],"architectures":[35],"using":[36],"pipelined":[37],"memory":[38,51,96],"controllers":[40],"can":[41,55,66],"be":[42,56],"generated.":[43],"this":[45],"paper,":[46],"we":[47],"focus":[48],"on":[49],"implementing":[50],"interfacing":[52],"modules":[53],"that":[54],"automatically":[57],"generated":[58],"from":[59,88],"high-level":[61],"synthesis":[62],"tool":[63],"which":[65],"efficiently":[67],"handle":[68],"predictable":[69],"address":[70,79,86],"well":[73,102],"random":[75],"ones":[76],"(i.e.,":[77],"dynamic":[78,85],"computations).":[80],"The":[81],"benefits":[82],"balancing":[84],"computations":[87],"datapath":[89],"to":[90,110],"dedicated":[91],"computation":[92],"units":[93],"in":[94],"the":[95],"controller":[97],"is":[98],"also":[99],"analyzed":[100],"operator":[104],"bitwidth":[105],"optimization":[106],"locality":[109],"save":[111],"power":[112],"consumption":[113],"reduce":[115],"latency.":[116]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":4}],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}
