{"id":"https://openalex.org/W1966460777","doi":"https://doi.org/10.1109/tvlsi.2008.2000364","title":"Profit Aware Circuit Design Under Process Variations Considering Speed Binning","display_name":"Profit Aware Circuit Design Under Process Variations Considering Speed Binning","publication_year":2008,"publication_date":"2008-07-01","ids":{"openalex":"https://openalex.org/W1966460777","doi":"https://doi.org/10.1109/tvlsi.2008.2000364","mag":"1966460777"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2008.2000364","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2000364","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065043481","display_name":"Animesh Datta","orcid":"https://orcid.org/0000-0003-4021-4655"},"institutions":[{"id":"https://openalex.org/I19268510","display_name":"Qualcomm (United Kingdom)","ror":"https://ror.org/04d3djg48","country_code":"GB","type":"company","lineage":["https://openalex.org/I19268510","https://openalex.org/I4210087596"]},{"id":"https://openalex.org/I4210087596","display_name":"Qualcomm (United States)","ror":"https://ror.org/002zrf773","country_code":"US","type":"company","lineage":["https://openalex.org/I4210087596"]},{"id":"https://openalex.org/I4210111675","display_name":"Market Matters","ror":"https://ror.org/021yan307","country_code":"US","type":"nonprofit","lineage":["https://openalex.org/I4210111675"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Animesh Datta","raw_affiliation_strings":["Qualcomm, Inc., San Diego, CA, USA","[QUALCOMM Inc., San Diego, CA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Qualcomm, Inc., San Diego, CA, USA","institution_ids":["https://openalex.org/I4210087596"]},{"raw_affiliation_string":"[QUALCOMM Inc., San Diego, CA]","institution_ids":["https://openalex.org/I19268510","https://openalex.org/I4210111675"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039442844","display_name":"Swarup Bhunia","orcid":"https://orcid.org/0000-0001-6082-6961"},"institutions":[{"id":"https://openalex.org/I58956616","display_name":"Case Western Reserve University","ror":"https://ror.org/051fd9666","country_code":"US","type":"education","lineage":["https://openalex.org/I58956616"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Swarup Bhunia","raw_affiliation_strings":["Electrical Engineering and Computer Science Department, Case Western Reserve University, Cleveland, OH, USA","Electrical Engineering and Computer Science Department, Case Western Reserve University, Cleveland, OH#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering and Computer Science Department, Case Western Reserve University, Cleveland, OH, USA","institution_ids":["https://openalex.org/I58956616"]},{"raw_affiliation_string":"Electrical Engineering and Computer Science Department, Case Western Reserve University, Cleveland, OH#TAB#","institution_ids":["https://openalex.org/I58956616"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103231030","display_name":"Jung Hwan Choi","orcid":"https://orcid.org/0009-0009-4976-9930"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jung Hwan Choi","raw_affiliation_strings":["Electrical and Computer Engineering Department, Purdue University, West Lafayette, IN, USA","Electrical and Computer Engineering Department, Purdue University, West Lafayette, IN"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Electrical and Computer Engineering Department, Purdue University, West Lafayette, IN","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009591041","display_name":"Saibal Mukhopadhyay","orcid":"https://orcid.org/0000-0002-8894-3390"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Saibal Mukhopadhyay","raw_affiliation_strings":["Electrical and Computer Engineering Department, Georgia Institute of Technology, Atlanta, GA, USA","Electrical and Computer Engineering Department, Georgia Institute of Technology, Atlanta, GA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"Electrical and Computer Engineering Department, Georgia Institute of Technology, Atlanta, GA#TAB#","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046257293","display_name":"Kaushik Roy","orcid":"https://orcid.org/0000-0003-4937-2115"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kaushik Roy","raw_affiliation_strings":["Electrical and Computer Engineering Department, Purdue University, West Lafayette, IN, USA","Electrical and Computer Engineering Department, Purdue University, West Lafayette, IN"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Electrical and Computer Engineering Department, Purdue University, West Lafayette, IN","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.3742,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.87896279,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"16","issue":"7","first_page":"806","last_page":"815"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.7524683475494385},{"id":"https://openalex.org/keywords/bin","display_name":"Bin","score":0.5701593160629272},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5358210206031799},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4940932095050812},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4928596019744873},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.48847973346710205},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45622286200523376},{"id":"https://openalex.org/keywords/profit","display_name":"Profit (economics)","score":0.44882282614707947},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.4476616680622101},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4316096901893616},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.41813692450523376},{"id":"https://openalex.org/keywords/performance-metric","display_name":"Performance metric","score":0.41356921195983887},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.3872810900211334},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.31318116188049316},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.25463515520095825},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1791803538799286}],"concepts":[{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.7524683475494385},{"id":"https://openalex.org/C156273044","wikidata":"https://www.wikidata.org/wiki/Q4913766","display_name":"Bin","level":2,"score":0.5701593160629272},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5358210206031799},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4940932095050812},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4928596019744873},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.48847973346710205},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45622286200523376},{"id":"https://openalex.org/C181622380","wikidata":"https://www.wikidata.org/wiki/Q26911","display_name":"Profit (economics)","level":2,"score":0.44882282614707947},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.4476616680622101},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4316096901893616},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.41813692450523376},{"id":"https://openalex.org/C2780898871","wikidata":"https://www.wikidata.org/wiki/Q860554","display_name":"Performance metric","level":2,"score":0.41356921195983887},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.3872810900211334},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.31318116188049316},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.25463515520095825},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1791803538799286},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C175444787","wikidata":"https://www.wikidata.org/wiki/Q39072","display_name":"Microeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C187736073","wikidata":"https://www.wikidata.org/wiki/Q2920921","display_name":"Management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2008.2000364","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2000364","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1498699371","https://openalex.org/W2006589289","https://openalex.org/W2033443176","https://openalex.org/W2035894108","https://openalex.org/W2048470475","https://openalex.org/W2104726505","https://openalex.org/W2117648153","https://openalex.org/W2123009614","https://openalex.org/W2123021960","https://openalex.org/W2123057190","https://openalex.org/W2126564504","https://openalex.org/W2132389735","https://openalex.org/W2132554587","https://openalex.org/W2134067926","https://openalex.org/W2141907973","https://openalex.org/W2159874000","https://openalex.org/W2167253897","https://openalex.org/W4231119589","https://openalex.org/W4237955880","https://openalex.org/W4240704676","https://openalex.org/W4249223601","https://openalex.org/W4255738297"],"related_works":["https://openalex.org/W4253195573","https://openalex.org/W2020934033","https://openalex.org/W2070693700","https://openalex.org/W2743305891","https://openalex.org/W2126983197","https://openalex.org/W2908947570","https://openalex.org/W2374651972","https://openalex.org/W4309227549","https://openalex.org/W2078506771","https://openalex.org/W2134664711"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"a":[3,15,36,58,88,117],"profit-aware":[4],"design":[5,16,25,37,59,70,118],"metric":[6],"is":[7,27,51],"proposed":[8],"to":[9,30,53,79,116],"consider":[10],"the":[11,32],"overall":[12],"merit":[13,34],"of":[14,19,35,57,90],"in":[17,94,98,126],"terms":[18],"power":[20,110],"and":[21,41,75,103,112],"performance.":[22],"A":[23,45],"statistical":[24],"methodology":[26,71],"then":[28],"developed":[29,52],"improve":[31,54],"economic":[33,55],"considering":[38,107],"frequency":[39],"binning":[40],"product":[42],"price":[43],"profile.":[44],"low-complexity":[46],"sensitivity-based":[47],"gate":[48],"sizing":[49,74,102],"algorithm":[50],"gain":[56],"over":[60],"its":[61],"initial":[62],"yield-optimized":[63],"design.":[64],"Finally,":[65],"we":[66],"present":[67],"an":[68,83],"integrated":[69],"for":[72,100,121],"simultaneous":[73,101],"bin":[76,104],"boundary":[77,105],"determination":[78],"enhance":[80],"profit":[81,99],"under":[82],"area":[84],"constraint.":[85],"Experiments":[86],"on":[87],"set":[89],"ISCAS'85":[91],"benchmarks":[92],"show":[93],"average":[95],"19%":[96],"improvement":[97],"determination,":[106],"both":[108],"leakage":[109],"dissipation":[111],"delay":[113],"bounds":[114],"compared":[115],"initially":[119],"optimized":[120],"90%":[122],"yield":[123],"at":[124],"iso-area":[125],"70-nm":[127],"bulk":[128],"CMOS":[129],"technology.":[130]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
