{"id":"https://openalex.org/W2156476431","doi":"https://doi.org/10.1109/tvlsi.2008.2000256","title":"Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits","display_name":"Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits","publication_year":2008,"publication_date":"2008-05-20","ids":{"openalex":"https://openalex.org/W2156476431","doi":"https://doi.org/10.1109/tvlsi.2008.2000256","mag":"2156476431"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2008.2000256","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2000256","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103091913","display_name":"Chong Zhao","orcid":"https://orcid.org/0000-0001-7108-9311"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California, San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Chong Zhao","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California, San Diego, La Jolla, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California, San Diego, La Jolla, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037994687","display_name":"Zhao Yi","orcid":"https://orcid.org/0000-0002-0723-2301"},"institutions":[{"id":"https://openalex.org/I4210144218","display_name":"Orora Design Technologies (United States)","ror":"https://ror.org/04jhtcf60","country_code":"US","type":"company","lineage":["https://openalex.org/I4210144218"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yi Zhao","raw_affiliation_strings":["Orora Design Technologies, Inc., Kirkland, WA, USA"],"affiliations":[{"raw_affiliation_string":"Orora Design Technologies, Inc., Kirkland, WA, USA","institution_ids":["https://openalex.org/I4210144218"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5105369696","display_name":"Sujit Dey","orcid":"https://orcid.org/0000-0001-9671-3950"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California, San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sujit Dey","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California, San Diego, La Jolla, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California, San Diego, La Jolla, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5103091913"],"corresponding_institution_ids":["https://openalex.org/I36258959"],"apc_list":null,"apc_paid":null,"fwci":0.3329,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.66820888,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"16","issue":"6","first_page":"714","last_page":"724"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9923999905586243,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.7981354594230652},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6046677231788635},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.6019459366798401},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5820366144180298},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.5485523343086243},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5478163361549377},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5242547988891602},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.4998750686645508},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4607149064540863},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.451865017414093},{"id":"https://openalex.org/keywords/circuit-reliability","display_name":"Circuit reliability","score":0.42958173155784607},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3678697645664215},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.348888635635376},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24638652801513672},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.22597911953926086},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.18586724996566772},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.15396210551261902},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10259518027305603}],"concepts":[{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.7981354594230652},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6046677231788635},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.6019459366798401},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5820366144180298},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.5485523343086243},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5478163361549377},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5242547988891602},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.4998750686645508},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4607149064540863},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.451865017414093},{"id":"https://openalex.org/C2778309119","wikidata":"https://www.wikidata.org/wiki/Q5121614","display_name":"Circuit reliability","level":4,"score":0.42958173155784607},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3678697645664215},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.348888635635376},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24638652801513672},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.22597911953926086},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.18586724996566772},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.15396210551261902},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10259518027305603},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2008.2000256","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2000256","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W781445378","https://openalex.org/W1985238821","https://openalex.org/W2013185880","https://openalex.org/W2026329473","https://openalex.org/W2030501553","https://openalex.org/W2050431855","https://openalex.org/W2052461569","https://openalex.org/W2100219166","https://openalex.org/W2104122494","https://openalex.org/W2108298591","https://openalex.org/W2112352286","https://openalex.org/W2117115814","https://openalex.org/W2141068710","https://openalex.org/W2152162846","https://openalex.org/W2161033118","https://openalex.org/W2162465831","https://openalex.org/W2169213530","https://openalex.org/W2567458453","https://openalex.org/W2614099084","https://openalex.org/W2752885492","https://openalex.org/W3089273347","https://openalex.org/W3145128584","https://openalex.org/W4210496735","https://openalex.org/W4229966209","https://openalex.org/W6676147604","https://openalex.org/W6783633047"],"related_works":["https://openalex.org/W4283025278","https://openalex.org/W2158463942","https://openalex.org/W2116314988","https://openalex.org/W4390630982","https://openalex.org/W2394408226","https://openalex.org/W2116274229","https://openalex.org/W4389168214","https://openalex.org/W2991904152","https://openalex.org/W4366457933","https://openalex.org/W2332860651"],"abstract_inverted_index":{"Due":[0],"to":[1,11,20,67,130],"aggressive":[2],"technology":[3],"scaling,":[4],"VLSI":[5],"circuits":[6],"are":[7,34],"becoming":[8],"increasingly":[9],"susceptible":[10],"radiation-induced":[12],"single-event-upsets":[13],"(SEUs).":[14],"Redundancy":[15],"insertion":[16,161],"has":[17],"been":[18],"adopted":[19],"provide":[21],"the":[22,37,70,75,102,107,109,119,131,134,144,158,163,179,189,200],"circuit":[23],"with":[24,168],"additional":[25],"transient":[26],"error":[27,121,164],"resiliency.":[28],"However,":[29],"its":[30],"applicability":[31],"and":[32,41,127,152,172,183],"efficiency":[33],"limited":[35],"by":[36,166,177],"tight":[38],"design":[39,77,98,150,184,201],"constraints":[40,151],"budgets.":[42,153],"In":[43],"this":[44],"paper,":[45],"we":[46,186],"present":[47],"an":[48,138],"intelligent":[49,159],"ldquoconstraint-aware":[50],"robustness":[51,114,160],"insertionrdquo":[52],"methodology.":[53],"By":[54],"selectively":[55],"protecting":[56],"sequential":[57,96,125],"elements":[58,126],"in":[59],"static":[60],"CMOS":[61],"digital":[62],"circuits,":[63],"it":[64],"is":[65,92,112,137],"able":[66],"maximally":[68],"improve":[69],"SEU":[71],"tolerance":[72,122],"while":[73,198],"keeping":[74,199],"incurred":[76],"overhead":[78,202],"within":[79,203],"acceptable":[80,204],"range.":[81,205],"Our":[82],"technique":[83,116,191],"consists":[84],"of":[85,106,123],"three":[86],"major":[87],"components.":[88],"The":[89],"first":[90],"one":[91,111,136],"a":[93,113],"configurable":[94],"hardening":[95],"cell":[97],"that":[99,117,141,157],"serves":[100],"as":[101],"basic":[103],"building":[104],"block":[105],"framework;":[108],"second":[110],"calibration":[115],"evaluates":[118],"relative":[120],"all":[124],"provides":[128],"guidelines":[129],"redundancy":[132],"insertion;":[133],"third":[135],"optimization":[139],"algorithm":[140],"searches":[142],"for":[143],"optimal":[145],"protection":[146],"scheme":[147],"under":[148],"given":[149],"Simulation":[154],"results":[155],"show":[156],"reduced":[162],"rate":[165],"46%":[167],"zero":[169],"timing":[170],"penalty":[171],"10%":[173],"area":[174],"increase.":[175],"Furthermore,":[176],"exploring":[178],"tradeoffs":[180],"between":[181],"reliability":[182,196],"overhead,":[185],"also":[187],"demonstrate":[188],"proposed":[190],"can":[192],"help":[193],"achieve":[194],"high":[195],"improvement":[197]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}