{"id":"https://openalex.org/W3092521657","doi":"https://doi.org/10.1109/tvlsi.2008.2000248","title":"Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers","display_name":"Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers","publication_year":2008,"publication_date":"2008-05-20","ids":{"openalex":"https://openalex.org/W3092521657","doi":"https://doi.org/10.1109/tvlsi.2008.2000248","mag":"3092521657"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2008.2000248","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2000248","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111891819","display_name":"Ashutosh Chakraborty","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Ashutosh Chakraborty","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Turino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Turino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071452284","display_name":"K. Duraisami","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Karthik Duraisami","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Turino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Turino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006552035","display_name":"Ashoka Sathanur","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Ashoka Sathanur","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Turino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Turino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077409979","display_name":"P. Sithambaram","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Prassanna Sithambaram","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Turino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Turino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["Dipartimento di Elettronica, Informatica, e Sistemistica, Universit\u00e0 di Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Informatica, e Sistemistica, Universit\u00e0 di Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058379509","display_name":"Alberto Macii","orcid":"https://orcid.org/0000-0002-8869-5710"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Alberto Macii","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Turino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Turino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005432629","display_name":"Enrico Macii","orcid":"https://orcid.org/0000-0001-9046-5618"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Enrico Macii","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Turino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Turino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024891882","display_name":"Massimo Poncino","orcid":"https://orcid.org/0000-0002-1369-9688"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Massimo Poncino","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Turino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Turino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5111891819"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":5.66,"has_fulltext":false,"cited_by_count":48,"citation_normalized_percentile":{"value":0.96188086,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":"16","issue":"6","first_page":"639","last_page":"649"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.8393155336380005},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.6869460344314575},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.6583943367004395},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.6569995880126953},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.6419141888618469},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6295286417007446},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.6024889945983887},{"id":"https://openalex.org/keywords/compensation","display_name":"Compensation (psychology)","score":0.5246867537498474},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5243535041809082},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.5024287700653076},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.43005385994911194},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.4222361445426941},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.4126068949699402},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.31229013204574585},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.23073843121528625},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.18151837587356567},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17621415853500366},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08173024654388428}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.8393155336380005},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.6869460344314575},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.6583943367004395},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.6569995880126953},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.6419141888618469},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6295286417007446},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.6024889945983887},{"id":"https://openalex.org/C2780023022","wikidata":"https://www.wikidata.org/wiki/Q1338171","display_name":"Compensation (psychology)","level":2,"score":0.5246867537498474},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5243535041809082},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.5024287700653076},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.43005385994911194},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.4222361445426941},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.4126068949699402},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.31229013204574585},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.23073843121528625},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.18151837587356567},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17621415853500366},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08173024654388428},{"id":"https://openalex.org/C15744967","wikidata":"https://www.wikidata.org/wiki/Q9418","display_name":"Psychology","level":0,"score":0.0},{"id":"https://openalex.org/C11171543","wikidata":"https://www.wikidata.org/wiki/Q41630","display_name":"Psychoanalysis","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2008.2000248","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2008.2000248","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:cris.unibo.it:11585/62271","is_oa":false,"landing_page_url":"http://hdl.handle.net/11585/62271","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5199999809265137,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W1480877791","https://openalex.org/W1500653364","https://openalex.org/W1514437667","https://openalex.org/W1558331362","https://openalex.org/W1714959240","https://openalex.org/W2014853465","https://openalex.org/W2062554267","https://openalex.org/W2064189791","https://openalex.org/W2098228187","https://openalex.org/W2117648153","https://openalex.org/W2119986070","https://openalex.org/W2128876681","https://openalex.org/W2130765643","https://openalex.org/W2132816157","https://openalex.org/W2136047350","https://openalex.org/W2136768070","https://openalex.org/W2138548848","https://openalex.org/W2141686413","https://openalex.org/W2142850552","https://openalex.org/W2146351359","https://openalex.org/W2160913524","https://openalex.org/W2173972090","https://openalex.org/W4230442644","https://openalex.org/W4234913381","https://openalex.org/W4237096326","https://openalex.org/W4238535529","https://openalex.org/W4239466105","https://openalex.org/W4243059613","https://openalex.org/W4247586331","https://openalex.org/W4249004757","https://openalex.org/W4250643412","https://openalex.org/W4253995697"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W2144282137","https://openalex.org/W2127892766","https://openalex.org/W3006003651","https://openalex.org/W2617666058","https://openalex.org/W2090213929","https://openalex.org/W2148462217","https://openalex.org/W2165139624"],"abstract_inverted_index":{"The":[0,34],"thermal":[1,57],"gradients":[2],"existing":[3],"in":[4,13,93,149,154],"high-performance":[5],"circuits":[6],"may":[7],"significantly":[8],"affect":[9],"their":[10,172],"timing":[11],"behavior,":[12],"particular,":[14],"by":[15,109,121,134],"increasing":[16],"the":[17,20,29,37,62,85,90,111,117,136,140,155,163],"skew":[18,184],"of":[19,36,40,61,87,104,165,196],"clock":[21,49,63,91,118,183],"net":[22],"and/or":[23],"altering":[24],"hold/setup":[25],"constraints,":[26],"possibly":[27],"causing":[28],"circuit":[30],"to":[31,45,54,139,161,178],"operate":[32],"incorrectly.":[33],"knowledge":[35],"spatial":[38],"distribution":[39,70],"temperature":[41,69],"can":[42,99],"be":[43],"used":[44],"properly":[46],"design":[47],"a":[48,95,150],"network":[50,64,119],"that":[51,97,113,182],"is":[52,65,71,107,144,185],"able":[53],"compensate":[55,100],"such":[56,94],"non-uniformities.":[58],"However,":[59],"redesign":[60],"effective":[66],"only":[67],"if":[68],"stationary,":[72],"i.e.,":[73],"does":[74],"not":[75],"change":[76],"over":[77],"time.":[78],"In":[79],"this":[80],"paper,":[81],"we":[82],"specifically":[83],"address":[84],"problem":[86],"dynamically":[88],"modifying":[89],"tree":[92],"way":[96],"it":[98],"for":[101],"temporal":[102],"variations":[103,130],"temperature.":[105],"This":[106],"achieved":[108],"exploiting":[110],"buffers":[112],"are":[114,131],"inserted":[115,153,166],"during":[116],"generation,":[120],"transforming":[122],"them":[123],"into":[124],"tunable":[125,141,167,173],"delay":[126,129],"elements.":[127],"Temperature-induced":[128],"then":[132],"compensated":[133],"applying":[135],"proper":[137],"tuning":[138,151],"buffers,":[142,168],"which":[143],"computed":[145],"offline":[146],"and":[147,193,198],"stored":[148],"table":[152],"design.":[156],"We":[157],"propose":[158],"an":[159],"algorithm":[160],"minimize":[162],"number":[164],"as":[169,171],"well":[170],"range":[174],"(which":[175],"directly":[176],"relates":[177],"complexity).":[179],"Results":[180],"show":[181],"kept":[186],"within":[187],"original":[188],"bounds":[189],"with":[190],"worst-case":[191],"power":[192],"area":[194],"penalty":[195],"3.5%":[197],"5.5%":[199],"respectively.":[200]},"counts_by_year":[{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":7},{"year":2014,"cited_by_count":6},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}