{"id":"https://openalex.org/W2117439128","doi":"https://doi.org/10.1109/tvlsi.2002.1043339","title":"An ultra-fast instruction set simulator","display_name":"An ultra-fast instruction set simulator","publication_year":2002,"publication_date":"2002-06-01","ids":{"openalex":"https://openalex.org/W2117439128","doi":"https://doi.org/10.1109/tvlsi.2002.1043339","mag":"2117439128"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2002.1043339","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2002.1043339","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109246835","display_name":"Jianwen Zhu","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Jianwen Zhu","raw_affiliation_strings":["Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, University of Toronto, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada#TAB#","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025797692","display_name":"Daniel D. Gajski","orcid":null},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D.D. Gajski","raw_affiliation_strings":["Information and Computer Science, University of California, Irvine, CA, USA","Inf. & Comput. Sci., Univ. of California, Irvine, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Information and Computer Science, University of California, Irvine, CA, USA","institution_ids":["https://openalex.org/I204250578"]},{"raw_affiliation_string":"Inf. & Comput. Sci., Univ. of California, Irvine, CA","institution_ids":["https://openalex.org/I204250578"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.2517,"has_fulltext":false,"cited_by_count":34,"citation_normalized_percentile":{"value":0.88500486,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"10","issue":"3","first_page":"363","last_page":"373"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8219619989395142},{"id":"https://openalex.org/keywords/workstation","display_name":"Workstation","score":0.7736392021179199},{"id":"https://openalex.org/keywords/host","display_name":"Host (biology)","score":0.666077733039856},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.6498203873634338},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.6278003454208374},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.6250110864639282},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.526792585849762},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5007772445678711},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4897449016571045},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.4494818449020386},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3961087763309479},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.22625228762626648}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8219619989395142},{"id":"https://openalex.org/C67953723","wikidata":"https://www.wikidata.org/wiki/Q192525","display_name":"Workstation","level":2,"score":0.7736392021179199},{"id":"https://openalex.org/C126831891","wikidata":"https://www.wikidata.org/wiki/Q221673","display_name":"Host (biology)","level":2,"score":0.666077733039856},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.6498203873634338},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.6278003454208374},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.6250110864639282},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.526792585849762},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5007772445678711},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4897449016571045},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4494818449020386},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3961087763309479},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.22625228762626648},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2002.1043339","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2002.1043339","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4099999964237213,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1492257710","https://openalex.org/W1501834527","https://openalex.org/W1567646530","https://openalex.org/W1582039972","https://openalex.org/W1861934346","https://openalex.org/W1999421692","https://openalex.org/W2018016444","https://openalex.org/W2073418263","https://openalex.org/W2089131124","https://openalex.org/W2117588798","https://openalex.org/W2143374918","https://openalex.org/W2161925862","https://openalex.org/W2163033792","https://openalex.org/W2163935347","https://openalex.org/W2168555828","https://openalex.org/W2339669378","https://openalex.org/W2519134721","https://openalex.org/W4212802658","https://openalex.org/W4232896609","https://openalex.org/W4245834773","https://openalex.org/W4247082178","https://openalex.org/W4256204637","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W1998013902","https://openalex.org/W2550108858","https://openalex.org/W4247993032","https://openalex.org/W2120424507","https://openalex.org/W1781968824","https://openalex.org/W3145476088","https://openalex.org/W2117274229","https://openalex.org/W1963867998","https://openalex.org/W3002622661","https://openalex.org/W2058198174"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"present":[4],"new":[5],"techniques":[6],"which":[7,46],"further":[8],"improve":[9],"the":[10,19,23,43,58,91,95,98,101],"static":[11],"compilation-based":[12],"instruction":[13],"set":[14],"architecture":[15],"(ISA)":[16],"simulation":[17,59],"by":[18,31],"aggressive":[20],"utilization":[21,28],"of":[22,63,69,103],"host":[24,96],"machine":[25],"resources.":[26],"Such":[27],"is":[29,83],"achieved":[30],"defining":[32],"a":[33,50,61,76],"low-level":[34],"code-generation":[35,51],"interface":[36],"specialized":[37],"for":[38],"ISA":[39],"simulation,":[40],"rather":[41],"than":[42,90],"traditional":[44],"approaches":[45],"use":[47],"C":[48],"as":[49],"interface.":[52],"We":[53],"are":[54],"able":[55],"to":[56,65,100],"perform":[57],"at":[60],"speed":[62],"up":[64],"10/sup":[66],"2/":[67],"millions":[68],"simulated":[70],"instructions":[71],"per":[72],"second":[73],"(MIPS)":[74],"on":[75,85,94],"270":[77],"MHz":[78],"Ultra-5":[79],"workstation.":[80],"This":[81],"result":[82],"only":[84],"average":[86],"1.6":[87],"times":[88],"slower":[89],"native":[92],"execution":[93],"machine,":[97],"fastest":[99],"best":[102],"our":[104],"knowledge.":[105]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
