{"id":"https://openalex.org/W2158818923","doi":"https://doi.org/10.1109/tvlsi.2002.1043338","title":"Vertically integrated SOI circuits for low-power and high-performance applications","display_name":"Vertically integrated SOI circuits for low-power and high-performance applications","publication_year":2002,"publication_date":"2002-06-01","ids":{"openalex":"https://openalex.org/W2158818923","doi":"https://doi.org/10.1109/tvlsi.2002.1043338","mag":"2158818923"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2002.1043338","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2002.1043338","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101012313","display_name":"Liqiong Wei","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Liqiong Wei","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050177970","display_name":"Rongtian Zhang","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rongtian Zhang","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031161187","display_name":"Kaushik Roy","orcid":"https://orcid.org/0009-0002-3375-2877"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Roy","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071255345","display_name":"Zhanping Chen","orcid":"https://orcid.org/0000-0002-2844-459X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhanping Chen","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004290377","display_name":"David B. Janes","orcid":"https://orcid.org/0000-0002-1482-7485"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D.B. Janes","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5101012313"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":1.3578,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.82136019,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"10","issue":"3","first_page":"351","last_page":"362"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10361","display_name":"Silicon Carbide Semiconductor Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/silicon-on-insulator","display_name":"Silicon on insulator","score":0.8545470237731934},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5965791344642639},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5831829309463501},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.552098274230957},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5198814868927002},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5091249346733093},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.49548232555389404},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.48987075686454773},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.4195801317691803},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.37833303213119507},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.3682754635810852},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3379339575767517},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.30865567922592163},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.287261039018631},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2731027603149414},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.17663925886154175},{"id":"https://openalex.org/keywords/silicon","display_name":"Silicon","score":0.12312641739845276},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10202610492706299},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.08919495344161987},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.06738269329071045}],"concepts":[{"id":"https://openalex.org/C53143962","wikidata":"https://www.wikidata.org/wiki/Q1478788","display_name":"Silicon on insulator","level":3,"score":0.8545470237731934},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5965791344642639},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5831829309463501},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.552098274230957},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5198814868927002},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5091249346733093},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.49548232555389404},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.48987075686454773},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.4195801317691803},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.37833303213119507},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.3682754635810852},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3379339575767517},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.30865567922592163},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.287261039018631},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2731027603149414},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.17663925886154175},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.12312641739845276},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10202610492706299},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.08919495344161987},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.06738269329071045},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2002.1043338","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2002.1043338","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6399999856948853,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1528549966","https://openalex.org/W1556480701","https://openalex.org/W1562507966","https://openalex.org/W1569581024","https://openalex.org/W1606828151","https://openalex.org/W1849248634","https://openalex.org/W2000107694","https://openalex.org/W2014007884","https://openalex.org/W2036347478","https://openalex.org/W2073864521","https://openalex.org/W2087552937","https://openalex.org/W2099904601","https://openalex.org/W2102412728","https://openalex.org/W2112234144","https://openalex.org/W2120062652","https://openalex.org/W2132333170","https://openalex.org/W2133800303","https://openalex.org/W2136172476","https://openalex.org/W2140039917","https://openalex.org/W2153376746","https://openalex.org/W2154774982","https://openalex.org/W2497389460","https://openalex.org/W2534881376","https://openalex.org/W2543097326","https://openalex.org/W3148448013","https://openalex.org/W4234319728"],"related_works":["https://openalex.org/W2149263014","https://openalex.org/W2071492559","https://openalex.org/W1999169921","https://openalex.org/W2141708460","https://openalex.org/W2033631699","https://openalex.org/W2442246590","https://openalex.org/W2109072162","https://openalex.org/W2037897954","https://openalex.org/W2541239502","https://openalex.org/W2538802758"],"abstract_inverted_index":{"Vertical":[0],"integration":[1,28,49,170],"offers":[2],"numerous":[3],"advantages":[4],"over":[5],"conventional":[6],"structures.":[7],"By":[8],"stacking":[9,19],"multiple-material":[10],"layers":[11,22],"to":[12,23,59,122,182],"form":[13,24],"double":[14,74],"gate":[15,75,124],"transistors":[16],"and":[17,38,55,63,67,80,82,102,120,141],"by":[18,174],"multiple":[20],"device":[21,61],"multidevice-layer":[25,84],"integration,":[26],"vertical":[27,48],"can":[29,50,188],"emerge":[30],"as":[31],"the":[32,47,98,156,176],"technology":[33],"of":[34,71,100,111,184],"choice":[35],"for":[36,97,165,191],"low-power":[37,167],"high-performance":[39],"integration.":[40,194],"In":[41],"this":[42],"paper,":[43],"we":[44],"demonstrate":[45],"that":[46,150,180],"achieve":[51],"better":[52],"circuit":[53,107,144],"performance":[54,145,172,186],"power":[56,109],"dissipation":[57,110],"due":[58],"improved":[60],"characteristics":[62],"reduced":[64],"interconnect":[65,185],"complexity":[66],"delay.":[68],"The":[69],"structures":[70],"vertically":[72],"integrated":[73],"(DG)":[76],"silicon-on-insulator":[77],"(SOI)":[78],"devices":[79],"circuits,":[81],"corresponding":[83],"(3-D)":[85],"SOI":[86,93,104,116,126,130,152],"circuits":[87,117,131,154],"are":[88,118,132,146],"presented;":[89],"a":[90,192],"general":[91],"double-gate":[92,112],"model":[94],"is":[95],"provided":[96],"study":[99],"symmetric":[101],"asymmetric":[103],"CMOS":[105,153],"circuits;":[106,127],"speed,":[108],"dynamic":[113],"threshold":[114],"(DGDT)":[115],"investigated":[119],"compared":[121],"single":[123],"(SG)":[125],"potential":[128],"3-D":[129],"laid":[133],"out.":[134],"Chip":[135],"area,":[136],"layout":[137],"complexity,":[138],"process":[139],"cost,":[140],"impact":[142],"on":[143],"studied.":[147],"Results":[148,178],"show":[149],"DGDT":[151],"provide":[155],"best":[157],"power-delay":[158],"product,":[159],"which":[160],"makes":[161],"them":[162],"very":[163],"attractive":[164],"low-voltage":[166],"applications.":[168],"Multidevice-layer":[169],"achieves":[171],"improvement":[173],"shortening":[175],"interconnects.":[177],"indicate":[179],"up":[181],"40%":[183],"improvements":[187],"be":[189],"expected":[190],"4-device-layer":[193]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
