{"id":"https://openalex.org/W2152333735","doi":"https://doi.org/10.1109/tsp.2011.6043723","title":"Fractional frequency synthesizer using flying adder principle","display_name":"Fractional frequency synthesizer using flying adder principle","publication_year":2011,"publication_date":"2011-08-01","ids":{"openalex":"https://openalex.org/W2152333735","doi":"https://doi.org/10.1109/tsp.2011.6043723","mag":"2152333735"},"language":"en","primary_location":{"id":"doi:10.1109/tsp.2011.6043723","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tsp.2011.6043723","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 34th International Conference on Telecommunications and Signal Processing (TSP)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5046281598","display_name":"Milan \u0160tork","orcid":"https://orcid.org/0000-0001-5028-3473"},"institutions":[{"id":"https://openalex.org/I92715842","display_name":"University of West Bohemia","ror":"https://ror.org/040t43x18","country_code":"CZ","type":"education","lineage":["https://openalex.org/I92715842"]}],"countries":["CZ"],"is_corresponding":true,"raw_author_name":"Milan Stork","raw_affiliation_strings":["Regional Innovation Centre for Electrical Engineering, University of West Bohemia, Plzen, Czech Republic"],"affiliations":[{"raw_affiliation_string":"Regional Innovation Centre for Electrical Engineering, University of West Bohemia, Plzen, Czech Republic","institution_ids":["https://openalex.org/I92715842"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5046281598"],"corresponding_institution_ids":["https://openalex.org/I92715842"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16317539,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"35","issue":null,"first_page":"294","last_page":"297"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9926000237464905,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9146461486816406},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6598668098449707},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5889290571212769},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.5690048336982727},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5606431365013123},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.51873379945755},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.48831531405448914},{"id":"https://openalex.org/keywords/simple","display_name":"Simple (philosophy)","score":0.48095837235450745},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.46401748061180115},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.42690715193748474},{"id":"https://openalex.org/keywords/integer","display_name":"Integer (computer science)","score":0.4222649931907654},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21276536583900452},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.17068758606910706},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.16512858867645264},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.1484304964542389},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.11110919713973999}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9146461486816406},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6598668098449707},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5889290571212769},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.5690048336982727},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5606431365013123},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.51873379945755},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.48831531405448914},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.48095837235450745},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.46401748061180115},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.42690715193748474},{"id":"https://openalex.org/C97137487","wikidata":"https://www.wikidata.org/wiki/Q729138","display_name":"Integer (computer science)","level":2,"score":0.4222649931907654},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21276536583900452},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.17068758606910706},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16512858867645264},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.1484304964542389},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.11110919713973999},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tsp.2011.6043723","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tsp.2011.6043723","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 34th International Conference on Telecommunications and Signal Processing (TSP)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/11","score":0.6100000143051147,"display_name":"Sustainable cities and communities"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320335322","display_name":"European Regional Development Fund","ror":"https://ror.org/00k4n6c32"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W2029583434","https://openalex.org/W2041062586","https://openalex.org/W2059713124","https://openalex.org/W2101326734","https://openalex.org/W2109748401","https://openalex.org/W2110635581","https://openalex.org/W2142192225","https://openalex.org/W2166998732","https://openalex.org/W2167284852","https://openalex.org/W2171035445","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2015155483","https://openalex.org/W2359366503","https://openalex.org/W2330020385","https://openalex.org/W2371350995","https://openalex.org/W2161157531","https://openalex.org/W2350523680","https://openalex.org/W1973484824","https://openalex.org/W2376731877","https://openalex.org/W3145870900","https://openalex.org/W2375072050"],"abstract_inverted_index":{"The":[0,86],"frequency":[1,74],"synthesis":[2],"is":[3,34,54,59],"one":[4,38],"of":[5,17,47],"the":[6,15,23,48],"most":[7,10],"important":[8],"and":[9,81],"actively":[11],"researched":[12],"subjects":[13],"in":[14,26],"field":[16],"VLSI":[18],"mixed-signal":[19],"circuit":[20],"design.":[21],"Among":[22],"existing":[24],"techniques":[25],"this":[27,90],"area,":[28],"phase":[29,82],"locked":[30,83],"loop":[31,84],"fractional":[32,73],"architecture":[33,53,76],"a":[35,62],"widely":[36],"used":[37],"for":[39],"generating":[40],"frequencies":[41],"which":[42,58],"are":[43,92],"not":[44],"integer":[45],"multiple":[46],"input":[49],"reference":[50],"frequency.":[51],"Flying-Adder":[52],"an":[55],"emerging":[56],"technique":[57],"based":[60,77],"on":[61,78],"new":[63],"concept":[64,79],"time-average-frequency,":[65],"to":[66],"generate":[67],"frequencies.":[68],"This":[69],"paper":[70],"presents":[71],"simple":[72],"synthesizer":[75],"flying-adder":[80],"principle.":[85],"simulation":[87],"results":[88],"concerning":[89],"approach":[91],"presented.":[93]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
