{"id":"https://openalex.org/W7147626427","doi":"https://doi.org/10.1109/tr.2026.3679968","title":"A Dual-Mode Online BISR Architecture for Interconnect and Memory Repair in Chiplet-Based Systems","display_name":"A Dual-Mode Online BISR Architecture for Interconnect and Memory Repair in Chiplet-Based Systems","publication_year":2026,"publication_date":"2026-01-01","ids":{"openalex":"https://openalex.org/W7147626427","doi":"https://doi.org/10.1109/tr.2026.3679968"},"language":null,"primary_location":{"id":"doi:10.1109/tr.2026.3679968","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tr.2026.3679968","pdf_url":null,"source":{"id":"https://openalex.org/S87725633","display_name":"IEEE Transactions on Reliability","issn_l":"0018-9529","issn":["0018-9529","1558-1721"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Reliability","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065997728","display_name":"Donghyun Han","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Donghyun Han","raw_affiliation_strings":["Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"],"raw_orcid":"https://orcid.org/0000-0002-2385-2375","affiliations":[{"raw_affiliation_string":"Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045379772","display_name":"Sooryeong Lee","orcid":"https://orcid.org/0009-0002-1669-3692"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Sooryeong Lee","raw_affiliation_strings":["Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"],"raw_orcid":"https://orcid.org/0009-0002-1669-3692","affiliations":[{"raw_affiliation_string":"Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044141196","display_name":"Jongho Park","orcid":"https://orcid.org/0000-0003-3718-4352"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jongho Park","raw_affiliation_strings":["Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"],"raw_orcid":"https://orcid.org/0000-0003-3718-4352","affiliations":[{"raw_affiliation_string":"Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020177318","display_name":"D K Kim","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Dayoung Kim","raw_affiliation_strings":["Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"],"raw_orcid":"https://orcid.org/0009-0002-6740-8919","affiliations":[{"raw_affiliation_string":"Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019872968","display_name":"S. Y. Kim","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Seungtae Kim","raw_affiliation_strings":["Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"],"raw_orcid":"https://orcid.org/0009-0006-9170-7969","affiliations":[{"raw_affiliation_string":"Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018704855","display_name":"Youngkwang Lee","orcid":"https://orcid.org/0000-0002-0732-4716"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Youngkwang Lee","raw_affiliation_strings":["Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5125239623","display_name":"S M Kang","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Sungho Kang","raw_affiliation_strings":["Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"],"raw_orcid":"https://orcid.org/0000-0002-7093-2095","affiliations":[{"raw_affiliation_string":"Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I193775966"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.32712212,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"75","issue":null,"first_page":"1525","last_page":"1539"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.19220000505447388,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.19220000505447388,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11661","display_name":"Copper Interconnects and Reliability","score":0.17810000479221344,"subfield":{"id":"https://openalex.org/subfields/2504","display_name":"Electronic, Optical and Magnetic Materials"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.1517000049352646,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.6535000205039978},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6492999792098999},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5285000205039978},{"id":"https://openalex.org/keywords/resilience","display_name":"Resilience (materials science)","score":0.4440000057220459},{"id":"https://openalex.org/keywords/fault-detection-and-isolation","display_name":"Fault detection and isolation","score":0.4334000051021576},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.429500013589859},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.38940000534057617},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.38920000195503235},{"id":"https://openalex.org/keywords/root-cause","display_name":"Root cause","score":0.32499998807907104}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.6535000205039978},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6492999792098999},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6449000239372253},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6338000297546387},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5285000205039978},{"id":"https://openalex.org/C2779585090","wikidata":"https://www.wikidata.org/wiki/Q3457762","display_name":"Resilience (materials science)","level":2,"score":0.4440000057220459},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.4334000051021576},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.429500013589859},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.38940000534057617},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.38920000195503235},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38920000195503235},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3555999994277954},{"id":"https://openalex.org/C84945661","wikidata":"https://www.wikidata.org/wiki/Q7366567","display_name":"Root cause","level":2,"score":0.32499998807907104},{"id":"https://openalex.org/C23725684","wikidata":"https://www.wikidata.org/wiki/Q616377","display_name":"Maintenance engineering","level":2,"score":0.314300000667572},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.30140000581741333},{"id":"https://openalex.org/C2775941552","wikidata":"https://www.wikidata.org/wiki/Q25212305","display_name":"Isolation (microbiology)","level":2,"score":0.3012000024318695},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.29670000076293945},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.29319998621940613},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.29190000891685486},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.2854999899864197},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.28200000524520874},{"id":"https://openalex.org/C2776638159","wikidata":"https://www.wikidata.org/wiki/Q18343761","display_name":"Memory cell","level":4,"score":0.27889999747276306},{"id":"https://openalex.org/C2776321774","wikidata":"https://www.wikidata.org/wiki/Q891131","display_name":"Read-write memory","level":3,"score":0.2759999930858612},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27379998564720154},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.273499995470047},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.27320000529289246},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.2711000144481659},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.26660001277923584},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.2635999917984009},{"id":"https://openalex.org/C7166840","wikidata":"https://www.wikidata.org/wiki/Q1199682","display_name":"System testing","level":2,"score":0.2597000002861023},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.25859999656677246},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.2540000081062317}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tr.2026.3679968","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tr.2026.3679968","pdf_url":null,"source":{"id":"https://openalex.org/S87725633","display_name":"IEEE Transactions on Reliability","issn_l":"0018-9529","issn":["0018-9529","1558-1721"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Reliability","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Chiplet-based":[0],"systems":[1],"provide":[2],"a":[3,47,166],"scalable":[4,168],"platform":[5],"for":[6,54,170],"heterogeneous":[7],"integration,":[8],"but":[9],"permanent":[10,113],"faults":[11,64,102,118,126],"in":[12],"interconnects":[13],"and":[14,42,57,62,68,94,105,149,162],"memory":[15,63],"cells":[16],"challenge":[17],"their":[18],"reliability.":[19,173],"While":[20],"standards":[21],"like":[22],"Universal":[23],"Chiplet":[24],"Interconnect":[25],"Express":[26],"(UCIe)":[27],"employ":[28],"single-domain":[29],"system":[30],"Error":[31],"Correction":[32],"Code":[33],"(ECC)":[34],"simplify":[35],"architecture,":[36],"they":[37],"often":[38],"limit":[39],"fault":[40],"isolation":[41],"recovery.":[43],"This":[44],"paper":[45],"proposes":[46],"dual-mode":[48,163],"Online":[49],"Built-In":[50],"Self-Repair":[51],"(OBISR)":[52],"architecture":[53],"unified":[55],"detection":[56],"repair":[58],"of":[59,85,108],"both":[60,129],"interconnect":[61,125],"during":[65],"post-bond":[66],"testing":[67],"in-field":[69],"operation.":[70],"Unlike":[71],"conventional":[72,157],"methods":[73],"that":[74,141],"merely":[75],"expand":[76],"ECC":[77,109],"capacity,":[78],"the":[79,82,132,142],"OBISR":[80,143],"targets":[81],"root":[83],"causes":[84],"persistent":[86],"errors":[87],"by":[88,147,153],"repurposing":[89],"existing":[90],"Content-Addressable":[91],"Memory":[92,117],"(CAM)":[93],"pathfinding":[95],"logic.":[96],"A":[97],"hierarchical":[98],"CAM":[99],"structure":[100],"classifies":[101],"using":[103],"spatial":[104],"recurrence":[106],"patterns":[107],"metadata":[110],"to":[111,134,156],"distinguish":[112],"defects":[114],"from":[115],"transients.":[116],"are":[119,127],"masked":[120],"via":[121],"logical":[122],"redirection,":[123],"while":[124],"rerouted,":[128],"operating":[130],"outside":[131],"datapath":[133],"ensure":[135],"zero":[136],"performance":[137],"degradation.":[138],"Evaluations":[139],"demonstrate":[140],"improves":[144],"system-level":[145],"resilience":[146],"235.49%":[148],"reduces":[150],"hardware":[151],"area":[152],"16.69%":[154],"compared":[155],"schemes.":[158],"Its":[159],"integrated":[160],"dual-domain":[161],"capabilities":[164],"offer":[165],"robust,":[167],"solution":[169],"next-generation":[171],"chiplet":[172]},"counts_by_year":[],"updated_date":"2026-04-17T05:58:53.018234","created_date":"2026-04-02T00:00:00"}