{"id":"https://openalex.org/W2563413695","doi":"https://doi.org/10.1109/tpds.2016.2645219","title":"Lightweight Virtual Memory Support for Zero-Copy Sharing of Pointer-Rich Data Structures in Heterogeneous Embedded SoCs","display_name":"Lightweight Virtual Memory Support for Zero-Copy Sharing of Pointer-Rich Data Structures in Heterogeneous Embedded SoCs","publication_year":2016,"publication_date":"2016-12-26","ids":{"openalex":"https://openalex.org/W2563413695","doi":"https://doi.org/10.1109/tpds.2016.2645219","mag":"2563413695"},"language":"en","primary_location":{"id":"doi:10.1109/tpds.2016.2645219","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tpds.2016.2645219","pdf_url":null,"source":{"id":"https://openalex.org/S97130795","display_name":"IEEE Transactions on Parallel and Distributed Systems","issn_l":"1045-9219","issn":["1045-9219","1558-2183","2161-9883"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Parallel and Distributed Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/11380/1171871","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5086250379","display_name":"Pirmin Vogel","orcid":"https://orcid.org/0000-0002-9657-736X"},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Pirmin Vogel","raw_affiliation_strings":["Integrated Systems Laboratory, ETH Zurich, Zurich, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, ETH Zurich, Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061145921","display_name":"Andrea Marongiu","orcid":"https://orcid.org/0000-0003-1010-4762"},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]},{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["CH","IT"],"is_corresponding":false,"raw_author_name":"Andrea Marongiu","raw_affiliation_strings":["Electrical, Electronic, and Information Engineering Department of the University of Bologna, Bologna, Italy","Integrated Systems Laboratory, ETH Zurich, Zurich, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical, Electronic, and Information Engineering Department of the University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"Integrated Systems Laboratory, ETH Zurich, Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]},{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["CH","IT"],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["Electrical, Electronic, and Information Engineering Department of the University of Bologna, Bologna, Italy","Integrated Systems Laboratory, ETH Zurich, Zurich, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical, Electronic, and Information Engineering Department of the University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"Integrated Systems Laboratory, ETH Zurich, Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":3.5603,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.92462312,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":88,"max":98},"biblio":{"volume":"28","issue":"7","first_page":"1947","last_page":"1959"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8087642192840576},{"id":"https://openalex.org/keywords/pointer","display_name":"Pointer (user interface)","score":0.5871478319168091},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47827064990997314},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.43401381373405457},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.42089757323265076},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.4077868163585663},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39210790395736694},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3566470742225647},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32785892486572266},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.2683790922164917}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8087642192840576},{"id":"https://openalex.org/C150202949","wikidata":"https://www.wikidata.org/wiki/Q107602","display_name":"Pointer (user interface)","level":2,"score":0.5871478319168091},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47827064990997314},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.43401381373405457},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.42089757323265076},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4077868163585663},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39210790395736694},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3566470742225647},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32785892486572266},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.2683790922164917}],"mesh":[],"locations_count":5,"locations":[{"id":"doi:10.1109/tpds.2016.2645219","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tpds.2016.2645219","pdf_url":null,"source":{"id":"https://openalex.org/S97130795","display_name":"IEEE Transactions on Parallel and Distributed Systems","issn_l":"1045-9219","issn":["1045-9219","1558-2183","2161-9883"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Parallel and Distributed Systems","raw_type":"journal-article"},{"id":"pmh:oai:cris.unibo.it:11585/613668","is_oa":false,"landing_page_url":"http://hdl.handle.net/11585/613668","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:iris.unimore.it:11380/1171871","is_oa":true,"landing_page_url":"http://hdl.handle.net/11380/1171871","pdf_url":null,"source":{"id":"https://openalex.org/S4306400718","display_name":"IRIS UNIMORE (University of Modena and Reggio Emilia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I122346577","host_organization_name":"University of Modena and Reggio Emilia","host_organization_lineage":["https://openalex.org/I122346577"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:www.research-collection.ethz.ch:20.500.11850/124602","is_oa":true,"landing_page_url":"http://hdl.handle.net/20.500.11850/124602","pdf_url":null,"source":{"id":"https://openalex.org/S4306402302","display_name":"Repository for Publications and Research Data (ETH Zurich)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I35440088","host_organization_name":"ETH Zurich","host_organization_lineage":["https://openalex.org/I35440088"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Transactions on Parallel and Distributed Systems, 28 (7)","raw_type":"info:eu-repo/semantics/article"},{"id":"doi:10.3929/ethz-b-000124602","is_oa":true,"landing_page_url":"https://doi.org/10.3929/ethz-b-000124602","pdf_url":null,"source":{"id":"https://openalex.org/S7407051236","display_name":"ETH Z\u00fcrich Research Collection","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Other"}],"best_oa_location":{"id":"pmh:oai:iris.unimore.it:11380/1171871","is_oa":true,"landing_page_url":"http://hdl.handle.net/11380/1171871","pdf_url":null,"source":{"id":"https://openalex.org/S4306400718","display_name":"IRIS UNIMORE (University of Modena and Reggio Emilia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I122346577","host_organization_name":"University of Modena and Reggio Emilia","host_organization_lineage":["https://openalex.org/I122346577"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G23525044","display_name":null,"funder_award_id":"FP7-611016","funder_id":"https://openalex.org/F4320334960","funder_display_name":"Seventh Framework Programme"}],"funders":[{"id":"https://openalex.org/F4320333065","display_name":"Seventh Framework Programme","ror":null},{"id":"https://openalex.org/F4320334960","display_name":"Seventh Framework Programme","ror":"https://ror.org/00k4n6c32"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W1726624971","https://openalex.org/W1970825693","https://openalex.org/W1974927420","https://openalex.org/W1990852260","https://openalex.org/W1994999558","https://openalex.org/W1997113918","https://openalex.org/W2010802738","https://openalex.org/W2020733012","https://openalex.org/W2028192447","https://openalex.org/W2037639500","https://openalex.org/W2047012348","https://openalex.org/W2057995607","https://openalex.org/W2059816505","https://openalex.org/W2062430565","https://openalex.org/W2066636486","https://openalex.org/W2099480851","https://openalex.org/W2100926301","https://openalex.org/W2128653745","https://openalex.org/W2135931458","https://openalex.org/W2288555998","https://openalex.org/W2329547742","https://openalex.org/W2342906597","https://openalex.org/W2402549220","https://openalex.org/W3097096317","https://openalex.org/W4232751114","https://openalex.org/W4244002525","https://openalex.org/W4256629673","https://openalex.org/W6637586930","https://openalex.org/W6696436358"],"related_works":["https://openalex.org/W1997145140","https://openalex.org/W1579905825","https://openalex.org/W2154371368","https://openalex.org/W2132940544","https://openalex.org/W2624061386","https://openalex.org/W2523870901","https://openalex.org/W2123237263","https://openalex.org/W2137976240","https://openalex.org/W2008437460","https://openalex.org/W3167332351"],"abstract_inverted_index":{"While":[0],"high-end":[1],"heterogeneous":[2,7,60],"systems":[3],"are":[4],"increasingly":[5],"supporting":[6],"uniform":[8],"memory":[9,21,54],"access":[10],"(hUMA),":[11],"their":[12],"low-power":[13],"counterparts":[14],"still":[15],"lack":[16],"basic":[17],"features":[18],"like":[19],"virtual":[20,53],"support":[22,55],"for":[23,51,56],"accelerators.":[24],"Instead":[25],"of":[26,93,101],"simply":[27],"passing":[28],"pointers,":[29],"explicit":[30],"data":[31,103],"management":[32],"involving":[33],"copies":[34],"is":[35,88],"needed":[36],"which":[37],"hampers":[38],"programmability":[39],"and":[40,76,97],"performance.":[41],"In":[42],"this":[43],"work,":[44],"we":[45],"evaluate":[46],"a":[47,72],"mixed":[48],"hardware/software":[49],"solution":[50,87],"lightweight":[52],"many-core":[57],"accelerators":[58],"in":[59],"embedded":[61],"systems-on-chip.":[62],"Based":[63],"on":[64],"an":[65],"input/output":[66],"translation":[67],"lookaside":[68],"buffer":[69],"managed":[70],"by":[71],"host":[73],"kernel-level":[74],"driver,":[75],"compiler":[77],"extensions":[78],"protecting":[79],"the":[80,91,94],"accelerator's":[81],"accesses":[82],"to":[83,90],"shared":[84],"data,":[85],"our":[86],"non-intrusive":[89],"architecture":[92],"accelerator":[95],"cores,":[96],"enables":[98],"zero-copy":[99],"sharing":[100],"pointer-rich":[102],"structures.":[104]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":3}],"updated_date":"2026-08-27T14:10:00.468798","created_date":"2025-10-10T00:00:00"}