{"id":"https://openalex.org/W2316468985","doi":"https://doi.org/10.1109/tpds.2016.2546246","title":"Using Switchable Pins to Increase Off-Chip Bandwidth in Chip-Multiprocessors","display_name":"Using Switchable Pins to Increase Off-Chip Bandwidth in Chip-Multiprocessors","publication_year":2016,"publication_date":"2016-03-24","ids":{"openalex":"https://openalex.org/W2316468985","doi":"https://doi.org/10.1109/tpds.2016.2546246","mag":"2316468985"},"language":"en","primary_location":{"id":"doi:10.1109/tpds.2016.2546246","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tpds.2016.2546246","pdf_url":null,"source":{"id":"https://openalex.org/S97130795","display_name":"IEEE Transactions on Parallel and Distributed Systems","issn_l":"1045-9219","issn":["1045-9219","1558-2183","2161-9883"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Parallel and Distributed Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103180705","display_name":"Shaoming Chen","orcid":"https://orcid.org/0009-0001-2420-7722"},"institutions":[{"id":"https://openalex.org/I121820613","display_name":"Louisiana State University","ror":"https://ror.org/05ect4e57","country_code":"US","type":"education","lineage":["https://openalex.org/I121820613"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Shaoming Chen","raw_affiliation_strings":["Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, Baton Rouge, LA","Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, Baton Rouge, LA#TAB#"],"affiliations":[{"raw_affiliation_string":"Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, Baton Rouge, LA","institution_ids":["https://openalex.org/I121820613"]},{"raw_affiliation_string":"Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, Baton Rouge, LA#TAB#","institution_ids":["https://openalex.org/I121820613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023542357","display_name":"Samuel Irving","orcid":null},"institutions":[{"id":"https://openalex.org/I121820613","display_name":"Louisiana State University","ror":"https://ror.org/05ect4e57","country_code":"US","type":"education","lineage":["https://openalex.org/I121820613"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Samuel Irving","raw_affiliation_strings":["Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, Baton Rouge, LA","Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, Baton Rouge, LA#TAB#"],"affiliations":[{"raw_affiliation_string":"Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, Baton Rouge, LA","institution_ids":["https://openalex.org/I121820613"]},{"raw_affiliation_string":"Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, Baton Rouge, LA#TAB#","institution_ids":["https://openalex.org/I121820613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101893942","display_name":"Lu Peng","orcid":"https://orcid.org/0000-0002-8579-5687"},"institutions":[{"id":"https://openalex.org/I121820613","display_name":"Louisiana State University","ror":"https://ror.org/05ect4e57","country_code":"US","type":"education","lineage":["https://openalex.org/I121820613"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lu Peng","raw_affiliation_strings":["Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, Baton Rouge, LA","Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, Baton Rouge, LA#TAB#"],"affiliations":[{"raw_affiliation_string":"Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, Baton Rouge, LA","institution_ids":["https://openalex.org/I121820613"]},{"raw_affiliation_string":"Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, Baton Rouge, LA#TAB#","institution_ids":["https://openalex.org/I121820613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057472134","display_name":"Yue Hu","orcid":"https://orcid.org/0000-0001-8959-6995"},"institutions":[{"id":"https://openalex.org/I121820613","display_name":"Louisiana State University","ror":"https://ror.org/05ect4e57","country_code":"US","type":"education","lineage":["https://openalex.org/I121820613"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yue Hu","raw_affiliation_strings":["Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, Baton Rouge, LA","Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, Baton Rouge, LA#TAB#"],"affiliations":[{"raw_affiliation_string":"Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, Baton Rouge, LA","institution_ids":["https://openalex.org/I121820613"]},{"raw_affiliation_string":"Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, Baton Rouge, LA#TAB#","institution_ids":["https://openalex.org/I121820613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100386112","display_name":"Ying Zhang","orcid":"https://orcid.org/0000-0002-2960-425X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ying Zhang","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA","Intel\u00ae Corporation, Santa Clara, CA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel\u00ae Corporation, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101810717","display_name":"Ashok Srivastava","orcid":"https://orcid.org/0000-0002-0357-2130"},"institutions":[{"id":"https://openalex.org/I121820613","display_name":"Louisiana State University","ror":"https://ror.org/05ect4e57","country_code":"US","type":"education","lineage":["https://openalex.org/I121820613"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ashok Srivastava","raw_affiliation_strings":["Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, Baton Rouge, LA","Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, Baton Rouge, LA#TAB#"],"affiliations":[{"raw_affiliation_string":"Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, Baton Rouge, LA","institution_ids":["https://openalex.org/I121820613"]},{"raw_affiliation_string":"Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, Baton Rouge, LA#TAB#","institution_ids":["https://openalex.org/I121820613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5103180705"],"corresponding_institution_ids":["https://openalex.org/I121820613"],"apc_list":null,"apc_paid":null,"fwci":0.6307,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.65196539,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":"28","issue":"1","first_page":"274","last_page":"289"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8282968401908875},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.6917951107025146},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6247037053108215},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.5779860019683838},{"id":"https://openalex.org/keywords/limiting","display_name":"Limiting","score":0.5333991050720215},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5277857184410095},{"id":"https://openalex.org/keywords/boosting","display_name":"Boosting (machine learning)","score":0.5015208721160889},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.4475586414337158},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4472337067127228},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4119688868522644},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.41036373376846313},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.37958723306655884},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.36202067136764526},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.3319573402404785},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3145391345024109},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.15487900376319885},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1516631543636322},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07575458288192749}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8282968401908875},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.6917951107025146},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6247037053108215},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.5779860019683838},{"id":"https://openalex.org/C188198153","wikidata":"https://www.wikidata.org/wiki/Q1613840","display_name":"Limiting","level":2,"score":0.5333991050720215},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5277857184410095},{"id":"https://openalex.org/C46686674","wikidata":"https://www.wikidata.org/wiki/Q466303","display_name":"Boosting (machine learning)","level":2,"score":0.5015208721160889},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.4475586414337158},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4472337067127228},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4119688868522644},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.41036373376846313},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37958723306655884},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36202067136764526},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.3319573402404785},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3145391345024109},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.15487900376319885},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1516631543636322},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07575458288192749},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tpds.2016.2546246","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tpds.2016.2546246","pdf_url":null,"source":{"id":"https://openalex.org/S97130795","display_name":"IEEE Transactions on Parallel and Distributed Systems","issn_l":"1045-9219","issn":["1045-9219","1558-2183","2161-9883"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Parallel and Distributed Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.7799999713897705}],"awards":[{"id":"https://openalex.org/G154938168","display_name":null,"funder_award_id":"CCF-1017961","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G7893912481","display_name":null,"funder_award_id":"CCF-1422408","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":38,"referenced_works":["https://openalex.org/W1546169179","https://openalex.org/W1636189610","https://openalex.org/W1963998358","https://openalex.org/W1967869476","https://openalex.org/W1979979548","https://openalex.org/W2003312212","https://openalex.org/W2080592089","https://openalex.org/W2098040113","https://openalex.org/W2100787464","https://openalex.org/W2102449048","https://openalex.org/W2114139104","https://openalex.org/W2118703320","https://openalex.org/W2120692212","https://openalex.org/W2129513794","https://openalex.org/W2129991978","https://openalex.org/W2132269953","https://openalex.org/W2134026160","https://openalex.org/W2135965542","https://openalex.org/W2138661001","https://openalex.org/W2139766816","https://openalex.org/W2144034023","https://openalex.org/W2145901239","https://openalex.org/W2147657366","https://openalex.org/W2147924310","https://openalex.org/W2147926533","https://openalex.org/W2151917022","https://openalex.org/W2157189715","https://openalex.org/W2162838417","https://openalex.org/W2163168517","https://openalex.org/W2165473669","https://openalex.org/W2166686159","https://openalex.org/W2170382128","https://openalex.org/W2273440736","https://openalex.org/W3140772298","https://openalex.org/W3144376511","https://openalex.org/W4247470640","https://openalex.org/W6681367006","https://openalex.org/W6694513646"],"related_works":["https://openalex.org/W2999459628","https://openalex.org/W2074563599","https://openalex.org/W3048967625","https://openalex.org/W1487697053","https://openalex.org/W2043352873","https://openalex.org/W1554378476","https://openalex.org/W2199439667","https://openalex.org/W1975698617","https://openalex.org/W2612219836","https://openalex.org/W4312264564"],"abstract_inverted_index":{"Off-chip":[0],"memory":[1,54,125,156,161],"bandwidth":[2,107,123],"has":[3],"been":[4],"considered":[5],"as":[6],"one":[7],"of":[8,13,28,38,69],"the":[9,64,67],"major":[10],"limiting":[11],"factors":[12],"processor":[14,22,41,48,70],"performance,":[15],"especially":[16],"for":[17,40,73,141,155],"multi-cores":[18],"and":[19],"many-cores.":[20],"Conventional":[21],"design":[23],"allocates":[24],"a":[25,35,47,99,160],"large":[26],"portion":[27],"off-chip":[29],"pins":[30,39,119],"to":[31,63,75,87,104,113,120,137],"deliver":[32],"power,":[33],"leaving":[34],"small":[36],"number":[37],"signal":[42],"communication.":[43],"We":[44],"observe":[45],"that":[46,66],"requires":[49],"much":[50],"less":[51],"power":[52,89,117],"during":[53,124],"intensive":[55,126,157],"stages":[56],"than":[57],"is":[58,61,111,135],"available.":[59],"This":[60,109,133],"due":[62],"fact":[65],"frequencies":[68],"cores":[71],"waiting":[72],"data":[74],"be":[76,82],"fetched":[77],"from":[78],"offchip":[79],"memories":[80],"can":[81],"scaled":[83],"down":[84],"in":[85],"order":[86],"save":[88],"without":[90],"degrading":[91],"performance.":[92,132],"Motivated":[93],"by":[94],"this":[95,106],"observation,":[96],"we":[97],"propose":[98],"dynamic":[100],"pin":[101],"switching":[102],"technique":[103,110],"alleviate":[105],"limitation.":[108],"introduced":[112],"dynamically":[114],"exploit":[115],"surplus":[116],"delivery":[118],"provide":[121],"extra":[122],"program":[127],"phases,":[128],"thereby":[129],"significantly":[130],"boosting":[131],"work":[134],"extended":[136],"compare":[138],"two":[139],"approaches":[140],"increasing":[142],"off":[143],"chip":[144],"bandwidths":[145],"using":[146,163],"switchable":[147],"pins.":[148],"Additionally,":[149],"it":[150],"shows":[151],"significant":[152],"performance":[153],"improvements":[154],"workloads":[158],"on":[159],"subsystem":[162],"Phase":[164],"Change":[165],"Memory.":[166]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
