{"id":"https://openalex.org/W2416993663","doi":"https://doi.org/10.1109/tpds.2015.2477841","title":"TLIA: Efficient Reconfigurable Architecture for Control-Intensive Kernels with Triggered-Long-Instructions","display_name":"TLIA: Efficient Reconfigurable Architecture for Control-Intensive Kernels with Triggered-Long-Instructions","publication_year":2015,"publication_date":"2015-09-10","ids":{"openalex":"https://openalex.org/W2416993663","doi":"https://doi.org/10.1109/tpds.2015.2477841","mag":"2416993663"},"language":"en","primary_location":{"id":"doi:10.1109/tpds.2015.2477841","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tpds.2015.2477841","pdf_url":null,"source":{"id":"https://openalex.org/S97130795","display_name":"IEEE Transactions on Parallel and Distributed Systems","issn_l":"1045-9219","issn":["1045-9219","1558-2183","2161-9883"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Parallel and Distributed Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100358856","display_name":"Leibo Liu","orcid":"https://orcid.org/0000-0001-7548-4116"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Leibo Liu","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062869202","display_name":"Junbin Wang","orcid":"https://orcid.org/0000-0002-2933-7892"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Junbin Wang","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102891205","display_name":"Jianfeng Zhu","orcid":"https://orcid.org/0000-0002-0485-8034"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianfeng Zhu","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023829435","display_name":"Chenchen Deng","orcid":null},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chenchen Deng","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":"https://orcid.org/0000-0003-1047-1087","affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054524841","display_name":"Shouyi Yin","orcid":"https://orcid.org/0000-0003-2309-572X"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shouyi Yin","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036023084","display_name":"Shaojun Wei","orcid":"https://orcid.org/0000-0001-5117-7920"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shaojun Wei","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.4344,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.86926056,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"27","issue":"7","first_page":"2143","last_page":"2154"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8908212184906006},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7028050422668457},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5845562815666199},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.5398904085159302},{"id":"https://openalex.org/keywords/control-flow","display_name":"Control flow","score":0.5173293948173523},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5157380700111389},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4967530369758606},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.44831424951553345},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.4255429804325104},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4129069447517395},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34787672758102417},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14621827006340027},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.13434067368507385}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8908212184906006},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7028050422668457},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5845562815666199},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.5398904085159302},{"id":"https://openalex.org/C160191386","wikidata":"https://www.wikidata.org/wiki/Q868299","display_name":"Control flow","level":2,"score":0.5173293948173523},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5157380700111389},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4967530369758606},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.44831424951553345},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.4255429804325104},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4129069447517395},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34787672758102417},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14621827006340027},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.13434067368507385},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tpds.2015.2477841","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tpds.2015.2477841","pdf_url":null,"source":{"id":"https://openalex.org/S97130795","display_name":"IEEE Transactions on Parallel and Distributed Systems","issn_l":"1045-9219","issn":["1045-9219","1558-2183","2161-9883"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Parallel and Distributed Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W105298322","https://openalex.org/W1964471912","https://openalex.org/W1989584178","https://openalex.org/W1990115841","https://openalex.org/W1997981962","https://openalex.org/W2006027340","https://openalex.org/W2015395294","https://openalex.org/W2027994226","https://openalex.org/W2028115839","https://openalex.org/W2039223206","https://openalex.org/W2047823179","https://openalex.org/W2074812550","https://openalex.org/W2082609830","https://openalex.org/W2086686503","https://openalex.org/W2089155985","https://openalex.org/W2107834734","https://openalex.org/W2117099910","https://openalex.org/W2121082877","https://openalex.org/W2122608448","https://openalex.org/W2137081678","https://openalex.org/W2138148495","https://openalex.org/W2138803271","https://openalex.org/W2316671010","https://openalex.org/W4231588404","https://openalex.org/W4235539633","https://openalex.org/W4242927735","https://openalex.org/W6604283553","https://openalex.org/W6662302268","https://openalex.org/W6676336487"],"related_works":["https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W1998013902","https://openalex.org/W2550108858","https://openalex.org/W1781968824","https://openalex.org/W4247993032","https://openalex.org/W3145476088","https://openalex.org/W2117274229","https://openalex.org/W1963867998"],"abstract_inverted_index":{"Coarse-Grained":[0],"Reconfigurable":[1],"Architectures":[2],"(CGRAs),":[3],"which":[4,110,142],"provide":[5],"high":[6],"performance,":[7],"low":[8],"power":[9,190],"and":[10,44,92,135,164,188],"flexibility,":[11],"is":[12,47,63,81,111,129,160,174,183,191],"viewed":[13],"as":[14],"a":[15,56],"promising":[16],"trend":[17],"for":[18,32],"computing.":[19],"CGRAs":[20],"are":[21,95],"mostly":[22],"employed":[23,82],"to":[24,40,65,178],"process":[25],"compute-intensive":[26],"kernels":[27],"because":[28],"of":[29,49,123,157],"their":[30],"inefficiency":[31],"control":[33,127,146],"flows.":[34],"Various":[35],"methods":[36],"have":[37,144],"been":[38],"proposed":[39,64,76],"alleviate":[41],"this":[42,54,88,119],"problem,":[43],"triggered":[45,68,78,140],"instruction":[46,79],"one":[48],"the":[50,67,75,99,114,121,172,181,189,197],"state-of-the-art":[51],"techniques.":[52],"In":[53,74,87,98,118],"paper,":[55],"reconfigurable":[57],"architecture":[58],"called":[59],"Triggered-Long-Instruction":[60],"Architecture":[61,201],"(TLIA)":[62],"enhance":[66],"instructions":[69,94,159],"with":[70,107],"parallel":[71,115],"condition":[72,116],"method.":[73,117],"architecture,":[77],"set":[80],"on":[83,151],"processing":[84],"elements":[85],"(PEs).":[86],"way,":[89,120],"over-serialized":[90],"execution":[91],"branch":[93],"both":[96],"eliminated.":[97],"meanwhile,":[100],"each":[101,126],"PE":[102],"has":[103],"an":[104],"improved":[105,175],"data-path":[106],"three":[108],"ALUs":[109],"inspired":[112],"by":[113,131,166,176,185,193],"amount":[122],"parallelism":[124],"inside":[125],"flow":[128],"increased":[130],"paralleling":[132],"predicate":[133],"computations":[134],"predicated":[136],"operations.":[137],"Moreover,":[138],"multiple":[139],"instructions,":[141],"may":[143],"internal":[145],"dependence,":[147],"can":[148],"be":[149],"executed":[150],"PEs":[152],"in":[153,162],"parallel.":[154],"The":[155],"strategy":[156],"issuing":[158],"implemented":[161],"hardware,":[163],"verified":[165],"FPGA.":[167],"Experimental":[168],"results":[169],"show":[170],"that":[171],"performance":[173],"20.9":[177],"140.0":[179],"percent,":[180,187],"area":[182],"reduced":[184,192],"24.5":[186],"32.5":[194],"percent":[195],"over":[196],"equivalent":[198],"Triggered":[199],"Instruction":[200],"(TIA).":[202]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2}],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}
