{"id":"https://openalex.org/W2317720307","doi":"https://doi.org/10.1109/tpds.2014.2345073","title":"Exploring Efficient Hardware Support for Applications with Irregular Memory Patterns on Multinode Manycore Architectures","display_name":"Exploring Efficient Hardware Support for Applications with Irregular Memory Patterns on Multinode Manycore Architectures","publication_year":2014,"publication_date":"2014-08-05","ids":{"openalex":"https://openalex.org/W2317720307","doi":"https://doi.org/10.1109/tpds.2014.2345073","mag":"2317720307"},"language":"en","primary_location":{"id":"doi:10.1109/tpds.2014.2345073","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tpds.2014.2345073","pdf_url":null,"source":{"id":"https://openalex.org/S97130795","display_name":"IEEE Transactions on Parallel and Distributed Systems","issn_l":"1045-9219","issn":["1045-9219","1558-2183","2161-9883"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Parallel and Distributed Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/11311/1026226","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049942674","display_name":"Marco Ceriani","orcid":"https://orcid.org/0000-0002-4498-5863"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Marco Ceriani","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy"],"raw_orcid":"https://orcid.org/0000-0002-4498-5863","affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081406299","display_name":"Simone Secchi","orcid":"https://orcid.org/0000-0002-8539-1578"},"institutions":[{"id":"https://openalex.org/I2801109035","display_name":"ARM (United Kingdom)","ror":"https://ror.org/04mmhzs81","country_code":"GB","type":"company","lineage":["https://openalex.org/I2801109035"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Simone Secchi","raw_affiliation_strings":["ARM Ltd, Cambridge, U.K"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ARM Ltd, Cambridge, U.K","institution_ids":["https://openalex.org/I2801109035"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111373927","display_name":"Oreste Villa","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Oreste Villa","raw_affiliation_strings":["NVIDIA Research, Santa Clara, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NVIDIA Research, Santa Clara, CA","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041853964","display_name":"Antonino Tumeo","orcid":"https://orcid.org/0000-0001-9452-120X"},"institutions":[{"id":"https://openalex.org/I1325736334","display_name":"Battelle","ror":"https://ror.org/01h5tnr73","country_code":"US","type":"nonprofit","lineage":["https://openalex.org/I1325736334"]},{"id":"https://openalex.org/I142606810","display_name":"Pacific Northwest National Laboratory","ror":"https://ror.org/05h992307","country_code":"US","type":"facility","lineage":["https://openalex.org/I1325736334","https://openalex.org/I1330989302","https://openalex.org/I142606810","https://openalex.org/I39565521"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Antonino Tumeo","raw_affiliation_strings":["High Performance Computing Group, Pacific Northwest National Laboratory, 902 Battelle Blvd, MSIN, Richland, WA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"High Performance Computing Group, Pacific Northwest National Laboratory, 902 Battelle Blvd, MSIN, Richland, WA","institution_ids":["https://openalex.org/I142606810","https://openalex.org/I1325736334"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077005193","display_name":"Gianluca Palermo","orcid":"https://orcid.org/0000-0001-7955-8012"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gianluca Palermo","raw_affiliation_strings":["Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5049942674"],"corresponding_institution_ids":["https://openalex.org/I93860229"],"apc_list":null,"apc_paid":null,"fwci":0.6301,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.72545176,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"28","issue":"6","first_page":"1635","last_page":"1648"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12292","display_name":"Graph Theory and Algorithms","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9072936177253723},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7032899856567383},{"id":"https://openalex.org/keywords/locality","display_name":"Locality","score":0.6281031370162964},{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.5832622051239014},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.5724382400512695},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.514509916305542},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5059482455253601},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.44804489612579346},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.1701945960521698},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1130826473236084}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9072936177253723},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7032899856567383},{"id":"https://openalex.org/C2779808786","wikidata":"https://www.wikidata.org/wiki/Q6664603","display_name":"Locality","level":2,"score":0.6281031370162964},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.5832622051239014},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.5724382400512695},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.514509916305542},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5059482455253601},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.44804489612579346},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.1701945960521698},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1130826473236084},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tpds.2014.2345073","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tpds.2014.2345073","pdf_url":null,"source":{"id":"https://openalex.org/S97130795","display_name":"IEEE Transactions on Parallel and Distributed Systems","issn_l":"1045-9219","issn":["1045-9219","1558-2183","2161-9883"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Parallel and Distributed Systems","raw_type":"journal-article"},{"id":"pmh:oai:re.public.polimi.it:11311/1026226","is_oa":true,"landing_page_url":"http://hdl.handle.net/11311/1026226","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:re.public.polimi.it:11311/1026226","is_oa":true,"landing_page_url":"http://hdl.handle.net/11311/1026226","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.46000000834465027,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":36,"referenced_works":["https://openalex.org/W152568512","https://openalex.org/W179815580","https://openalex.org/W1482680420","https://openalex.org/W1985131796","https://openalex.org/W1985662998","https://openalex.org/W2000604789","https://openalex.org/W2021685712","https://openalex.org/W2022740893","https://openalex.org/W2065413511","https://openalex.org/W2083400781","https://openalex.org/W2090409324","https://openalex.org/W2092070931","https://openalex.org/W2095760405","https://openalex.org/W2096544401","https://openalex.org/W2101117170","https://openalex.org/W2105996829","https://openalex.org/W2108170537","https://openalex.org/W2108321287","https://openalex.org/W2112722706","https://openalex.org/W2116652773","https://openalex.org/W2124861237","https://openalex.org/W2133250609","https://openalex.org/W2141662114","https://openalex.org/W2150669616","https://openalex.org/W2163715620","https://openalex.org/W2164554457","https://openalex.org/W2165301438","https://openalex.org/W2165487280","https://openalex.org/W2170616854","https://openalex.org/W2250844151","https://openalex.org/W3010061427","https://openalex.org/W4245607618","https://openalex.org/W4254869711","https://openalex.org/W6675437339","https://openalex.org/W6677496969","https://openalex.org/W6826325968"],"related_works":["https://openalex.org/W2355721938","https://openalex.org/W2387608311","https://openalex.org/W2086248387","https://openalex.org/W2973764441","https://openalex.org/W2350798290","https://openalex.org/W1542759904","https://openalex.org/W2114414746","https://openalex.org/W3090445364","https://openalex.org/W4255428424","https://openalex.org/W2057234250"],"abstract_inverted_index":{"With":[0],"computing":[1],"systems":[2],"becoming":[3,13],"ubiquitous,":[4],"numerous":[5],"data":[6,19,40,63],"sets":[7],"of":[8,50,79,98,115,133,147,168,174],"extremely":[9],"large":[10,53],"size":[11],"are":[12],"available":[14],"for":[15,58,171],"analysis.":[16],"Often":[17],"the":[18,36,39,44,48,128,145,148,153,156,166,169,175],"collected":[20],"have":[21],"complex,":[22],"graph":[23,162],"based":[24,90,163],"structures,":[25],"which":[26,103],"makes":[27],"them":[28],"difficult":[29],"to":[30,72,126],"process":[31],"with":[32,81,118,130],"traditional":[33],"tools.":[34],"Moreover,":[35],"irregularities":[37],"in":[38,43,52,155],"sets,":[41],"and":[42,61,100,112,150],"analysis":[45],"algorithms,":[46],"hamper":[47],"scaling":[49],"performance":[51],"distributed":[54,106],"high-performance":[55],"systems,":[56],"optimized":[57],"locality":[59],"exploitation":[60],"regular":[62],"structures.":[64],"In":[65],"this":[66],"paper":[67],"we":[68],"present":[69,139],"an":[70,140],"approach":[71,149],"system":[73],"design":[74,129],"that":[75,143],"enable":[76],"efficient":[77],"execution":[78],"applications":[80,164],"irregular":[82,135],"memory":[83],"patterns":[84],"on":[85,91,161],"a":[86,96,105,131],"distributed,":[87],"many-core":[88],"architecture,":[89],"off-the-shelf":[92],"cores.":[93],"We":[94,137],"introduce":[95],"set":[97,132],"hardware":[99],"software":[101],"components,":[102],"provide":[104],"global":[107],"address":[108],"space,":[109],"fine-grained":[110],"synchronization":[111],"latency":[113],"hiding":[114],"remote":[116],"accesses":[117],"multithreading.":[119],"An":[120],"FPGA":[121],"prototype":[122],"has":[123],"been":[124],"implemented":[125],"explore":[127],"typical":[134],"kernels.":[136],"finally":[138],"analytical":[141],"model":[142],"highlights":[144],"benefits":[146],"helps":[151],"identifying":[152],"bottlenecks":[154],"prototype.":[157],"The":[158],"experimental":[159],"evaluation":[160],"demonstrates":[165],"scalability":[167],"architecture":[170],"different":[172],"configurations":[173],"whole":[176],"system.":[177]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
