{"id":"https://openalex.org/W1978718503","doi":"https://doi.org/10.1109/tim.2014.2313431","title":"On System-on-Chip Testing Using Hybrid Test Vector Compression","display_name":"On System-on-Chip Testing Using Hybrid Test Vector Compression","publication_year":2014,"publication_date":"2014-05-16","ids":{"openalex":"https://openalex.org/W1978718503","doi":"https://doi.org/10.1109/tim.2014.2313431","mag":"1978718503"},"language":"en","primary_location":{"id":"doi:10.1109/tim.2014.2313431","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tim.2014.2313431","pdf_url":null,"source":{"id":"https://openalex.org/S10892749","display_name":"IEEE Transactions on Instrumentation and Measurement","issn_l":"0018-9456","issn":["0018-9456","1557-9662"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Instrumentation and Measurement","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109483458","display_name":"Satyendra N. Biswas","orcid":null},"institutions":[{"id":"https://openalex.org/I332121957","display_name":"Kaziranga University","ror":"https://ror.org/00vadgf54","country_code":"IN","type":"education","lineage":["https://openalex.org/I332121957"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Satyendra N. Biswas","raw_affiliation_strings":["Department of Electrical Engineering, Kaziranga University, Jorhat, Assam, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Kaziranga University, Jorhat, Assam, India","institution_ids":["https://openalex.org/I332121957"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103350095","display_name":"Sunil R. Das","orcid":null},"institutions":[{"id":"https://openalex.org/I149292303","display_name":"Troy University","ror":"https://ror.org/029jj9438","country_code":"US","type":"education","lineage":["https://openalex.org/I149292303"]},{"id":"https://openalex.org/I153718931","display_name":"University of Ottawa","ror":"https://ror.org/03c4mmv16","country_code":"CA","type":"education","lineage":["https://openalex.org/I153718931"]}],"countries":["CA","US"],"is_corresponding":false,"raw_author_name":"Sunil R. Das","raw_affiliation_strings":["Department of Computer Science, Troy University, Montgomery, AL, USA","School of Information Technology and Engineering, Faculty of Engineering, University of Ottawa, Ottawa, ON, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Troy University, Montgomery, AL, USA","institution_ids":["https://openalex.org/I149292303"]},{"raw_affiliation_string":"School of Information Technology and Engineering, Faculty of Engineering, University of Ottawa, Ottawa, ON, Canada","institution_ids":["https://openalex.org/I153718931"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023904661","display_name":"Emil M. Petriu","orcid":"https://orcid.org/0000-0002-0274-1035"},"institutions":[{"id":"https://openalex.org/I153718931","display_name":"University of Ottawa","ror":"https://ror.org/03c4mmv16","country_code":"CA","type":"education","lineage":["https://openalex.org/I153718931"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Emil M. Petriu","raw_affiliation_strings":["School of Information Technology and Engineering, Faculty of Engineering, University of Ottawa, Ottawa, ON, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Information Technology and Engineering, Faculty of Engineering, University of Ottawa, Ottawa, ON, Canada","institution_ids":["https://openalex.org/I153718931"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6302,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.6782883,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"63","issue":"11","first_page":"2611","last_page":"2619"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lossless-compression","display_name":"Lossless compression","score":0.658212423324585},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6313108801841736},{"id":"https://openalex.org/keywords/test-vector","display_name":"Test vector","score":0.5812518000602722},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5557994842529297},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5410600304603577},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5156310796737671},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.5155186653137207},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5043584108352661},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.4810467064380646},{"id":"https://openalex.org/keywords/data-compression","display_name":"Data compression","score":0.46300628781318665},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4443422555923462},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.4361097812652588},{"id":"https://openalex.org/keywords/integration-testing","display_name":"Integration testing","score":0.4298558831214905},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.4119339883327484},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3394627273082733},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.30837878584861755},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2910308539867401},{"id":"https://openalex.org/keywords/test-set","display_name":"Test set","score":0.2629719376564026},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.14337438344955444}],"concepts":[{"id":"https://openalex.org/C81081738","wikidata":"https://www.wikidata.org/wiki/Q55542","display_name":"Lossless compression","level":3,"score":0.658212423324585},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6313108801841736},{"id":"https://openalex.org/C100767440","wikidata":"https://www.wikidata.org/wiki/Q7705816","display_name":"Test vector","level":3,"score":0.5812518000602722},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5557994842529297},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5410600304603577},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5156310796737671},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.5155186653137207},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5043584108352661},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.4810467064380646},{"id":"https://openalex.org/C78548338","wikidata":"https://www.wikidata.org/wiki/Q2493","display_name":"Data compression","level":2,"score":0.46300628781318665},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4443422555923462},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4361097812652588},{"id":"https://openalex.org/C107683887","wikidata":"https://www.wikidata.org/wiki/Q782466","display_name":"Integration testing","level":3,"score":0.4298558831214905},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.4119339883327484},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3394627273082733},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.30837878584861755},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2910308539867401},{"id":"https://openalex.org/C169903167","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Test set","level":2,"score":0.2629719376564026},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.14337438344955444},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tim.2014.2313431","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tim.2014.2313431","pdf_url":null,"source":{"id":"https://openalex.org/S10892749","display_name":"IEEE Transactions on Instrumentation and Measurement","issn_l":"0018-9456","issn":["0018-9456","1557-9662"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Instrumentation and Measurement","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2801212107","display_name":null,"funder_award_id":"A 4750","funder_id":"https://openalex.org/F4320334593","funder_display_name":"Natural Sciences and Engineering Research Council of Canada"}],"funders":[{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W53492560","https://openalex.org/W1580506158","https://openalex.org/W1908802429","https://openalex.org/W1958365305","https://openalex.org/W2020404829","https://openalex.org/W2081587546","https://openalex.org/W2106186395","https://openalex.org/W2107745473","https://openalex.org/W2107800433","https://openalex.org/W2108140302","https://openalex.org/W2115613939","https://openalex.org/W2121745298","https://openalex.org/W2123064446","https://openalex.org/W2133595845","https://openalex.org/W2136670993","https://openalex.org/W2146594632","https://openalex.org/W2147419146","https://openalex.org/W2151335319","https://openalex.org/W2157702209","https://openalex.org/W2161488606","https://openalex.org/W2311244050","https://openalex.org/W2988216865","https://openalex.org/W4205527687","https://openalex.org/W4252188040","https://openalex.org/W4256464439","https://openalex.org/W6602169807","https://openalex.org/W6676050080"],"related_works":["https://openalex.org/W2053701592","https://openalex.org/W2138686808","https://openalex.org/W1749299286","https://openalex.org/W1996111092","https://openalex.org/W2149690470","https://openalex.org/W2075680532","https://openalex.org/W2569480541","https://openalex.org/W2444437806","https://openalex.org/W1959959029","https://openalex.org/W1978718503"],"abstract_inverted_index":{"This":[0,132],"paper":[1,133],"presents":[2],"a":[3,28,62,73],"comprehensive":[4],"hybrid":[5,63],"test":[6,42,53,100,107],"vector":[7],"compression":[8],"method":[9,71],"for":[10,79,104,125],"very":[11],"large":[12],"scale":[13],"integration":[14],"(VLSI)":[15],"circuit":[16],"testing,":[17],"targeting":[18],"specifically":[19],"embedded":[20,93,120],"cores-based":[21],"system-on-chips":[22],"(SoCs).":[23],"In":[24],"the":[25,34,40,52,68,92,97,105,118,139,143,146,153],"proposed":[26],"approach,":[27],"software":[29],"program":[30,85],"is":[31,56,102],"loaded":[32,90],"into":[33,67,91],"on-chip":[35,47,119],"processor":[36,121],"memory":[37],"along":[38],"with":[39,149],"compressed":[41],"data":[43,54,101],"sets.":[44],"To":[45],"minimize":[46],"storage":[48],"besides":[49],"testing":[50],"time,":[51],"volume":[55],"first":[57],"reduced":[58],"by":[59],"compaction":[60,84],"in":[61],"manner":[64],"before":[65],"downloading":[66],"processor.":[69],"The":[70,83,110],"uses":[72],"set":[74],"of":[75,99,130,138,145],"adaptive":[76],"coding":[77],"techniques":[78],"realizing":[80],"lossless":[81],"compression.":[82],"need":[86],"not":[87],"to":[88],"be":[89,123],"processor,":[94],"as":[95],"only":[96],"decompression":[98],"required":[103],"automatic":[106],"equipment":[108],"(ATE).":[109],"developed":[111],"scheme":[112],"necessitates":[113],"minimal":[114],"hardware":[115],"overhead,":[116],"while":[117],"can":[122],"reused":[124],"normal":[126],"operation":[127],"on":[128,136,152,156],"completion":[129],"testing.":[131],"reports":[134],"results":[135],"studies":[137],"problem":[140],"and":[141,158,163],"demonstrates":[142],"feasibility":[144],"suggested":[147],"methodology":[148],"simulation":[150],"runs":[151],"International":[154],"Symposium":[155],"Circuits":[157],"Systems":[159],"(ISCAS)":[160],"85":[161],"combinational":[162],"ISCAS":[164],"89":[165],"full-scan":[166],"sequential":[167],"benchmark":[168],"circuits.":[169]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}