{"id":"https://openalex.org/W1569323229","doi":"https://doi.org/10.1109/tii.2015.2449994","title":"Simplifying Many-Core-Based Heterogeneous SoC Programming With Offload Directives","display_name":"Simplifying Many-Core-Based Heterogeneous SoC Programming With Offload Directives","publication_year":2015,"publication_date":"2015-07-22","ids":{"openalex":"https://openalex.org/W1569323229","doi":"https://doi.org/10.1109/tii.2015.2449994","mag":"1569323229"},"language":"en","primary_location":{"id":"doi:10.1109/tii.2015.2449994","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tii.2015.2449994","pdf_url":null,"source":{"id":"https://openalex.org/S184777250","display_name":"IEEE Transactions on Industrial Informatics","issn_l":"1551-3203","issn":["1551-3203","1941-0050"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Industrial Informatics","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/11380/1171860","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061145921","display_name":"Andrea Marongiu","orcid":"https://orcid.org/0000-0003-1010-4762"},"institutions":[{"id":"https://openalex.org/I4210098188","display_name":"Laboratori Guglielmo Marconi (Italy)","ror":"https://ror.org/01r3vad87","country_code":"IT","type":"company","lineage":["https://openalex.org/I4210098188"]},{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]},{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH","IT"],"is_corresponding":true,"raw_author_name":"Andrea Marongiu","raw_affiliation_strings":["Department of Electrical, Electronic, and Information Engineering \u201cGuglielmo Marconi\u201d (DEI), University of Bologna, Bologna, Italy","Department of Information Technology and Electrical Engineering, Swiss Federal Institute of Technology Zurich (ETH Zurich), Zurich, Switzerland","[Department of Electrical, Electronic and Information Engineering, Guglielmo Marconi (DEI), University of Bologna, Bologna, Italy]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical, Electronic, and Information Engineering \u201cGuglielmo Marconi\u201d (DEI), University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I4210098188","https://openalex.org/I9360294"]},{"raw_affiliation_string":"Department of Information Technology and Electrical Engineering, Swiss Federal Institute of Technology Zurich (ETH Zurich), Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]},{"raw_affiliation_string":"[Department of Electrical, Electronic and Information Engineering, Guglielmo Marconi (DEI), University of Bologna, Bologna, Italy]","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023224638","display_name":"Alessandro Capotondi","orcid":"https://orcid.org/0000-0001-8705-0761"},"institutions":[{"id":"https://openalex.org/I4210098188","display_name":"Laboratori Guglielmo Marconi (Italy)","ror":"https://ror.org/01r3vad87","country_code":"IT","type":"company","lineage":["https://openalex.org/I4210098188"]},{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Alessandro Capotondi","raw_affiliation_strings":["Department of Electrical, Electronic, and Information Engineering \u201cGuglielmo Marconi\u201d (DEI), University of Bologna, Bologna, Italy","[Department of Electrical, Electronic and Information Engineering, Guglielmo Marconi (DEI), University of Bologna, Bologna, Italy]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical, Electronic, and Information Engineering \u201cGuglielmo Marconi\u201d (DEI), University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I4210098188","https://openalex.org/I9360294"]},{"raw_affiliation_string":"[Department of Electrical, Electronic and Information Engineering, Guglielmo Marconi (DEI), University of Bologna, Bologna, Italy]","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004842257","display_name":"Giuseppe Tagliavini","orcid":"https://orcid.org/0000-0002-9221-4633"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]},{"id":"https://openalex.org/I4210098188","display_name":"Laboratori Guglielmo Marconi (Italy)","ror":"https://ror.org/01r3vad87","country_code":"IT","type":"company","lineage":["https://openalex.org/I4210098188"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Giuseppe Tagliavini","raw_affiliation_strings":["Department of Electrical, Electronic, and Information Engineering \u201cGuglielmo Marconi\u201d (DEI), University of Bologna, Bologna, Italy","[Department of Electrical, Electronic and Information Engineering, Guglielmo Marconi (DEI), University of Bologna, Bologna, Italy]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical, Electronic, and Information Engineering \u201cGuglielmo Marconi\u201d (DEI), University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I4210098188","https://openalex.org/I9360294"]},{"raw_affiliation_string":"[Department of Electrical, Electronic and Information Engineering, Guglielmo Marconi (DEI), University of Bologna, Bologna, Italy]","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I4210098188","display_name":"Laboratori Guglielmo Marconi (Italy)","ror":"https://ror.org/01r3vad87","country_code":"IT","type":"company","lineage":["https://openalex.org/I4210098188"]},{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]},{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["CH","IT"],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["Department of Electrical, Electronic, and Information Engineering \u201cGuglielmo Marconi\u201d (DEI), University of Bologna, Bologna, Italy","Department of Information Technology and Electrical Engineering, Swiss Federal Institute of Technology Zurich (ETH Zurich), Zurich, Switzerland","[Department of Electrical, Electronic and Information Engineering, Guglielmo Marconi (DEI), University of Bologna, Bologna, Italy]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical, Electronic, and Information Engineering \u201cGuglielmo Marconi\u201d (DEI), University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I4210098188","https://openalex.org/I9360294"]},{"raw_affiliation_string":"Department of Information Technology and Electrical Engineering, Swiss Federal Institute of Technology Zurich (ETH Zurich), Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]},{"raw_affiliation_string":"[Department of Electrical, Electronic and Information Engineering, Guglielmo Marconi (DEI), University of Bologna, Bologna, Italy]","institution_ids":["https://openalex.org/I9360294"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5061145921"],"corresponding_institution_ids":["https://openalex.org/I35440088","https://openalex.org/I4210098188","https://openalex.org/I9360294"],"apc_list":null,"apc_paid":null,"fwci":4.6371,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":{"value":0.94691736,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"11","issue":"4","first_page":"957","last_page":"967"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8385173082351685},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.8072752356529236},{"id":"https://openalex.org/keywords/host","display_name":"Host (biology)","score":0.623184323310852},{"id":"https://openalex.org/keywords/programming-paradigm","display_name":"Programming paradigm","score":0.5909504890441895},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5232983231544495},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.5148200392723083},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5071988105773926},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4821760058403015},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4705280065536499},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.464526504278183},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.4309849143028259},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4251860976219177},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.42005980014801025},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.33778437972068787},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2498166859149933}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8385173082351685},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.8072752356529236},{"id":"https://openalex.org/C126831891","wikidata":"https://www.wikidata.org/wiki/Q221673","display_name":"Host (biology)","level":2,"score":0.623184323310852},{"id":"https://openalex.org/C34165917","wikidata":"https://www.wikidata.org/wiki/Q188267","display_name":"Programming paradigm","level":2,"score":0.5909504890441895},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5232983231544495},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.5148200392723083},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5071988105773926},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4821760058403015},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4705280065536499},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.464526504278183},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.4309849143028259},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4251860976219177},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.42005980014801025},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.33778437972068787},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2498166859149933},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tii.2015.2449994","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tii.2015.2449994","pdf_url":null,"source":{"id":"https://openalex.org/S184777250","display_name":"IEEE Transactions on Industrial Informatics","issn_l":"1551-3203","issn":["1551-3203","1941-0050"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Industrial Informatics","raw_type":"journal-article"},{"id":"pmh:oai:cris.unibo.it:11585/517281","is_oa":false,"landing_page_url":"http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7134757","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:iris.unimore.it:11380/1171860","is_oa":true,"landing_page_url":"http://hdl.handle.net/11380/1171860","pdf_url":null,"source":{"id":"https://openalex.org/S4306400718","display_name":"IRIS UNIMORE (University of Modena and Reggio Emilia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I122346577","host_organization_name":"University of Modena and Reggio Emilia","host_organization_lineage":["https://openalex.org/I122346577"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:iris.unimore.it:11380/1171860","is_oa":true,"landing_page_url":"http://hdl.handle.net/11380/1171860","pdf_url":null,"source":{"id":"https://openalex.org/S4306400718","display_name":"IRIS UNIMORE (University of Modena and Reggio Emilia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I122346577","host_organization_name":"University of Modena and Reggio Emilia","host_organization_lineage":["https://openalex.org/I122346577"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.41999998688697815}],"awards":[],"funders":[{"id":"https://openalex.org/F4320313987","display_name":"Universit\u00e0 degli Studi di Cagliari","ror":"https://ror.org/003109y17"},{"id":"https://openalex.org/F4320321652","display_name":"Eidgen\u00f6ssische Technische Hochschule Z\u00fcrich","ror":"https://ror.org/05a28rw58"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W518915","https://openalex.org/W141514224","https://openalex.org/W143948075","https://openalex.org/W1596133819","https://openalex.org/W1974927420","https://openalex.org/W1989761046","https://openalex.org/W1990383399","https://openalex.org/W1993641968","https://openalex.org/W1995433361","https://openalex.org/W2002555321","https://openalex.org/W2003526442","https://openalex.org/W2012295523","https://openalex.org/W2027390683","https://openalex.org/W2045886945","https://openalex.org/W2054591439","https://openalex.org/W2059015014","https://openalex.org/W2061388644","https://openalex.org/W2063877659","https://openalex.org/W2072989594","https://openalex.org/W2085358537","https://openalex.org/W2098426571","https://openalex.org/W2108103697","https://openalex.org/W2119010809","https://openalex.org/W2119485054","https://openalex.org/W2142677441","https://openalex.org/W2269751313","https://openalex.org/W3149771602","https://openalex.org/W4253914570","https://openalex.org/W6648871799","https://openalex.org/W6668879550"],"related_works":["https://openalex.org/W2502691491","https://openalex.org/W1976012348","https://openalex.org/W2002682434","https://openalex.org/W2137671689","https://openalex.org/W4387782849","https://openalex.org/W2012131147","https://openalex.org/W2113449380","https://openalex.org/W2157008728","https://openalex.org/W2092587530","https://openalex.org/W2153502022"],"abstract_inverted_index":{"Multiprocessor":[0],"systems-on-chip":[1],"(MPSoC)":[2],"are":[3,23],"evolving":[4],"into":[5],"heterogeneous":[6,17],"architectures":[7],"based":[8,43],"on":[9,44],"one":[10],"host":[11,56,102],"processor":[12],"plus":[13],"many-core":[14],"accelerators.":[15],"While":[16],"SoCs":[18],"promise":[19],"higher":[20],"performance/watt,":[21],"they":[22],"programmed":[24],"at":[25,90],"the":[26,51,71],"cost":[27],"of":[28,66],"major":[29],"code":[30],"rewrites":[31],"with":[32,46],"low-level":[33],"programming":[34,41,68,94],"abstractions":[35],"(e.g,":[36],"OpenCL).":[37],"We":[38,76],"present":[39],"a":[40,54,59,91],"model":[42,69],"OpenMP,":[45],"additional":[47],"directives":[48],"to":[49,86,98],"program":[50],"accelerator":[52],"from":[53],"single":[55],"program.":[57],"As":[58],"test":[60],"case,":[61],"we":[62],"evaluate":[63],"an":[64],"implementation":[65],"this":[67],"for":[70,80],"STMicroelectronics":[72],"STHORM":[73],"development":[74],"board.":[75],"obtain":[77],"near-ideal":[78],"throughput":[79],"most":[81],"benchmarks,":[82],"very":[83],"close":[84],"performance":[85],"hand-optimized":[87],"OpenCL":[88],"codes":[89],"significantly":[92],"lower":[93],"complexity,":[95],"and":[96],"up":[97],"30\u00d7":[99],"speedup":[100],"versus":[101],"execution":[103],"time.":[104]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":7},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-03-10T16:38:18.471706","created_date":"2016-06-24T00:00:00"}
