{"id":"https://openalex.org/W2002433278","doi":"https://doi.org/10.1109/tii.2012.2228871","title":"CAD Tools for Hardware Implementation of Embedded Fuzzy Systems on FPGAs","display_name":"CAD Tools for Hardware Implementation of Embedded Fuzzy Systems on FPGAs","publication_year":2012,"publication_date":"2012-11-21","ids":{"openalex":"https://openalex.org/W2002433278","doi":"https://doi.org/10.1109/tii.2012.2228871","mag":"2002433278"},"language":"en","primary_location":{"id":"doi:10.1109/tii.2012.2228871","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tii.2012.2228871","pdf_url":null,"source":{"id":"https://openalex.org/S184777250","display_name":"IEEE Transactions on Industrial Informatics","issn_l":"1551-3203","issn":["1551-3203","1941-0050"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Industrial Informatics","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004526273","display_name":"Mar\u00eda Brox","orcid":"https://orcid.org/0000-0002-4002-3253"},"institutions":[{"id":"https://openalex.org/I53110688","display_name":"University of C\u00f3rdoba","ror":"https://ror.org/05yc77b46","country_code":"ES","type":"education","lineage":["https://openalex.org/I53110688"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Maria Brox","raw_affiliation_strings":["Department of Computer Architecture, University of C\u00f3rdoba, C\u00f3rdoba, Spain","Dept. of Comput. Archit., Univ. of Cordoba, Cordoba, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Computer Architecture, University of C\u00f3rdoba, C\u00f3rdoba, Spain","institution_ids":["https://openalex.org/I53110688"]},{"raw_affiliation_string":"Dept. of Comput. Archit., Univ. of Cordoba, Cordoba, Spain","institution_ids":["https://openalex.org/I53110688"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033007233","display_name":"Santiago S\u00e1nchez-Solano","orcid":"https://orcid.org/0000-0002-0700-0447"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Santiago Sanchez-Solano","raw_affiliation_strings":["Instituto de Microelectr\u00f3nica de Sevilla (IMSE-CNM-CSIC), Seville, Spain","Inst. de Microelectron. de Sevilla (IMSE-CNM), Sevilla, Spain"],"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr\u00f3nica de Sevilla (IMSE-CNM-CSIC), Seville, Spain","institution_ids":["https://openalex.org/I4210104545"]},{"raw_affiliation_string":"Inst. de Microelectron. de Sevilla (IMSE-CNM), Sevilla, Spain","institution_ids":["https://openalex.org/I4210104545"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090302515","display_name":"Ernesto del Toro","orcid":null},"institutions":[{"id":"https://openalex.org/I908025542","display_name":"Polytechnic Jos\u00e9 Antonio Echeverr\u00eda","ror":"https://ror.org/0573cnq15","country_code":"CU","type":"education","lineage":["https://openalex.org/I908025542"]}],"countries":["CU"],"is_corresponding":false,"raw_author_name":"Ernesto del Toro","raw_affiliation_strings":["Microelectronics Research Center (CIME-CUJAE), Havana, Cuba","Microelectron. Res. Center (CIME-CUJAE), Havana, Cuba"],"affiliations":[{"raw_affiliation_string":"Microelectronics Research Center (CIME-CUJAE), Havana, Cuba","institution_ids":["https://openalex.org/I908025542"]},{"raw_affiliation_string":"Microelectron. Res. Center (CIME-CUJAE), Havana, Cuba","institution_ids":["https://openalex.org/I908025542"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056044825","display_name":"Piedad Brox","orcid":"https://orcid.org/0000-0003-1059-5338"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Piedad Brox","raw_affiliation_strings":["Instituto de Microelectr\u00f3nica de Sevilla (IMSE-CNM-CSIC), Seville, Spain","Inst. de Microelectron. de Sevilla (IMSE-CNM), Sevilla, Spain"],"affiliations":[{"raw_affiliation_string":"Instituto de Microelectr\u00f3nica de Sevilla (IMSE-CNM-CSIC), Seville, Spain","institution_ids":["https://openalex.org/I4210104545"]},{"raw_affiliation_string":"Inst. de Microelectron. de Sevilla (IMSE-CNM), Sevilla, Spain","institution_ids":["https://openalex.org/I4210104545"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033800254","display_name":"F.J. Moreno-Velo","orcid":"https://orcid.org/0000-0002-6108-6077"},"institutions":[{"id":"https://openalex.org/I78880903","display_name":"Universidad de Huelva","ror":"https://ror.org/03a1kt624","country_code":"ES","type":"education","lineage":["https://openalex.org/I78880903"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Francisco J. Moreno-Velo","raw_affiliation_strings":["Department of Applied Physics and Electrical Engineering, University of Huelva, Huelva, Spain","Dept. of Appl. Phys. & Electr. Eng., Univ. of Huelva, Huelva, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Applied Physics and Electrical Engineering, University of Huelva, Huelva, Spain","institution_ids":["https://openalex.org/I78880903"]},{"raw_affiliation_string":"Dept. of Appl. Phys. & Electr. Eng., Univ. of Huelva, Huelva, Spain","institution_ids":["https://openalex.org/I78880903"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5004526273"],"corresponding_institution_ids":["https://openalex.org/I53110688"],"apc_list":null,"apc_paid":null,"fwci":5.5659,"has_fulltext":false,"cited_by_count":29,"citation_normalized_percentile":{"value":0.95670313,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"9","issue":"3","first_page":"1635","last_page":"1644"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10820","display_name":"Fuzzy Logic and Control Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10820","display_name":"Fuzzy Logic and Control Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.993399977684021,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.8236817121505737},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8091673254966736},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6693861484527588},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6358053684234619},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6066568493843079},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5899685621261597},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.5747362971305847},{"id":"https://openalex.org/keywords/fuzzy-logic","display_name":"Fuzzy logic","score":0.5133713483810425},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.5045210123062134},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.48973560333251953},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4889132082462311},{"id":"https://openalex.org/keywords/fuzzy-electronics","display_name":"Fuzzy electronics","score":0.4715721011161804},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.4645260274410248},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.46143078804016113},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.44387441873550415},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.39469027519226074},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38157325983047485},{"id":"https://openalex.org/keywords/fuzzy-control-system","display_name":"Fuzzy control system","score":0.3470701575279236},{"id":"https://openalex.org/keywords/adaptive-neuro-fuzzy-inference-system","display_name":"Adaptive neuro fuzzy inference system","score":0.25034230947494507},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.22216951847076416},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.11244133114814758},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.10461682081222534}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.8236817121505737},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8091673254966736},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6693861484527588},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6358053684234619},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6066568493843079},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5899685621261597},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.5747362971305847},{"id":"https://openalex.org/C58166","wikidata":"https://www.wikidata.org/wiki/Q224821","display_name":"Fuzzy logic","level":2,"score":0.5133713483810425},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.5045210123062134},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.48973560333251953},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4889132082462311},{"id":"https://openalex.org/C102805184","wikidata":"https://www.wikidata.org/wiki/Q5511117","display_name":"Fuzzy electronics","level":5,"score":0.4715721011161804},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.4645260274410248},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.46143078804016113},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.44387441873550415},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.39469027519226074},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38157325983047485},{"id":"https://openalex.org/C195975749","wikidata":"https://www.wikidata.org/wiki/Q1475705","display_name":"Fuzzy control system","level":3,"score":0.3470701575279236},{"id":"https://openalex.org/C186108316","wikidata":"https://www.wikidata.org/wiki/Q352530","display_name":"Adaptive neuro fuzzy inference system","level":4,"score":0.25034230947494507},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.22216951847076416},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.11244133114814758},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.10461682081222534}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tii.2012.2228871","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tii.2012.2228871","pdf_url":null,"source":{"id":"https://openalex.org/S184777250","display_name":"IEEE Transactions on Industrial Informatics","issn_l":"1551-3203","issn":["1551-3203","1941-0050"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Industrial Informatics","raw_type":"journal-article"},{"id":"pmh:oai:idus.us.es:11441/76575","is_oa":false,"landing_page_url":"https://idus.us.es/handle//11441/76575","pdf_url":null,"source":{"id":"https://openalex.org/S4306400333","display_name":"idUS (Universidad de Sevilla)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79238269","host_organization_name":"Universidad de Sevilla","host_organization_lineage":["https://openalex.org/I79238269"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:digital.csic.es:10261/83677","is_oa":false,"landing_page_url":"http://hdl.handle.net/10261/83677","pdf_url":null,"source":{"id":"https://openalex.org/S4306400616","display_name":"DIGITAL.CSIC (Spanish National Research Council (CSIC))","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I134820265","host_organization_name":"Consejo Superior de Investigaciones Cient\u00edficas","host_organization_lineage":["https://openalex.org/I134820265"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"art\u00edculo"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5699999928474426,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":46,"referenced_works":["https://openalex.org/W204815715","https://openalex.org/W1677202527","https://openalex.org/W1717839947","https://openalex.org/W1719538838","https://openalex.org/W1751179731","https://openalex.org/W1971399800","https://openalex.org/W1988376612","https://openalex.org/W2014387502","https://openalex.org/W2033428986","https://openalex.org/W2037472804","https://openalex.org/W2037608282","https://openalex.org/W2041280856","https://openalex.org/W2086274107","https://openalex.org/W2100183523","https://openalex.org/W2101231061","https://openalex.org/W2109010302","https://openalex.org/W2111139814","https://openalex.org/W2112980318","https://openalex.org/W2113008369","https://openalex.org/W2114498885","https://openalex.org/W2117492699","https://openalex.org/W2118684782","https://openalex.org/W2125164397","https://openalex.org/W2130622494","https://openalex.org/W2136043916","https://openalex.org/W2156631632","https://openalex.org/W2161637059","https://openalex.org/W2162292398","https://openalex.org/W2162397979","https://openalex.org/W2166391214","https://openalex.org/W2167346087","https://openalex.org/W2168838895","https://openalex.org/W2291257309","https://openalex.org/W2482488034","https://openalex.org/W2484215240","https://openalex.org/W2501295153","https://openalex.org/W2540692632","https://openalex.org/W2545250969","https://openalex.org/W2799012172","https://openalex.org/W2809638548","https://openalex.org/W3121571934","https://openalex.org/W6637589901","https://openalex.org/W6660070333","https://openalex.org/W6684116818","https://openalex.org/W6696336027","https://openalex.org/W6788695199"],"related_works":["https://openalex.org/W2141004294","https://openalex.org/W2363829830","https://openalex.org/W2039193071","https://openalex.org/W35543821","https://openalex.org/W1515500413","https://openalex.org/W2097236935","https://openalex.org/W2366672283","https://openalex.org/W2127009070","https://openalex.org/W2064892006","https://openalex.org/W1988098726"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"two":[3,33],"computer-aided":[4],"design":[5,35,133],"(CAD)":[6],"tools":[7,17,77,90],"for":[8,22,78,104],"automatic":[9],"synthesis":[10,116],"of":[11,26,38,45,80,97,143,149],"fuzzy":[12,27,107,151],"logic-based":[13],"inference":[14,152],"systems.":[15,153],"The":[16,69],"share":[18],"a":[19,55,101],"common":[20],"architecture":[21],"efficient":[23],"hardware":[24],"implementation":[25],"modules,":[28],"but":[29],"are":[30,91],"based":[31],"on":[32,42,54,86],"different":[34],"strategies.":[36],"One":[37],"them":[39],"is":[40,100],"focused":[41],"the":[43,73,94,131,135,141],"generation":[44],"standard":[46],"VHDL":[47,115],"code,":[48],"which":[49,99],"can":[50],"be":[51],"later":[52],"implemented":[53],"reconfigurable":[56],"device":[57],"[field-programmable":[58],"gate":[59],"array":[60],"(FPGA)]":[61],"or":[62],"as":[63,120,122],"an":[64],"application-specific":[65],"integrated":[66],"circuit":[67],"(ASIC).":[68],"other":[70],"one":[71],"uses":[72],"Matlab/Simulink":[74],"environment":[75,103],"and":[76,109,117,146],"development":[79,126,137],"digital":[81],"signal":[82],"processing":[83],"(DSP)":[84],"systems":[85],"Xilinx's":[87],"FPGAs.":[88],"Both":[89],"included":[92,132],"in":[93],"last":[95],"version":[96],"Xfuzzy,":[98],"specific":[102],"designing":[105],"complex":[106],"systems,":[108],"they":[110],"provide":[111],"interfaces":[112],"to":[113,123],"commercial":[114],"verification":[118,148],"tools,":[119],"well":[121],"conventional":[124],"FPGA":[125],"environments.":[127],"As":[128],"demonstrated":[129],"by":[130],"example,":[134],"proposed":[136],"strategies":[138],"speed":[139],"up":[140],"stages":[142],"description,":[144],"synthesis,":[145],"functional":[147],"embedded":[150]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":8},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}