{"id":"https://openalex.org/W2021058029","doi":"https://doi.org/10.1109/tie.2014.2362888","title":"Architecture of FPGA Embedded Multiprocessor Programmable Controller","display_name":"Architecture of FPGA Embedded Multiprocessor Programmable Controller","publication_year":2014,"publication_date":"2014-10-14","ids":{"openalex":"https://openalex.org/W2021058029","doi":"https://doi.org/10.1109/tie.2014.2362888","mag":"2021058029"},"language":"en","primary_location":{"id":"doi:10.1109/tie.2014.2362888","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tie.2014.2362888","pdf_url":null,"source":{"id":"https://openalex.org/S58031724","display_name":"IEEE Transactions on Industrial Electronics","issn_l":"0278-0046","issn":["0278-0046","1557-9948"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Industrial Electronics","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040199805","display_name":"Z. Hajduk","orcid":"https://orcid.org/0000-0002-1375-7219"},"institutions":[{"id":"https://openalex.org/I111664937","display_name":"Rzesz\u00f3w University of Technology","ror":"https://ror.org/056xse072","country_code":"PL","type":"education","lineage":["https://openalex.org/I111664937"]}],"countries":["PL"],"is_corresponding":true,"raw_author_name":"Zbigniew Hajduk","raw_affiliation_strings":["Department of Computer and Control Engineering, Rzeszow University of Technology, Rzeszow, Poland"],"affiliations":[{"raw_affiliation_string":"Department of Computer and Control Engineering, Rzeszow University of Technology, Rzeszow, Poland","institution_ids":["https://openalex.org/I111664937"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071038915","display_name":"Bartosz Trybu\u015b","orcid":"https://orcid.org/0000-0002-4588-3973"},"institutions":[{"id":"https://openalex.org/I111664937","display_name":"Rzesz\u00f3w University of Technology","ror":"https://ror.org/056xse072","country_code":"PL","type":"education","lineage":["https://openalex.org/I111664937"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Bartosz Trybus","raw_affiliation_strings":["Department of Computer and Control Engineering, Rzeszow University of Technology, Rzeszow, Poland"],"affiliations":[{"raw_affiliation_string":"Department of Computer and Control Engineering, Rzeszow University of Technology, Rzeszow, Poland","institution_ids":["https://openalex.org/I111664937"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082371594","display_name":"Jan Sadolewski","orcid":"https://orcid.org/0000-0001-7370-9027"},"institutions":[{"id":"https://openalex.org/I111664937","display_name":"Rzesz\u00f3w University of Technology","ror":"https://ror.org/056xse072","country_code":"PL","type":"education","lineage":["https://openalex.org/I111664937"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Jan Sadolewski","raw_affiliation_strings":["Department of Computer and Control Engineering, Rzeszow University of Technology, Rzeszow, Poland"],"affiliations":[{"raw_affiliation_string":"Department of Computer and Control Engineering, Rzeszow University of Technology, Rzeszow, Poland","institution_ids":["https://openalex.org/I111664937"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5040199805"],"corresponding_institution_ids":["https://openalex.org/I111664937"],"apc_list":null,"apc_paid":null,"fwci":5.2101,"has_fulltext":false,"cited_by_count":46,"citation_normalized_percentile":{"value":0.95786766,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"62","issue":"5","first_page":"2952","last_page":"2961"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8833142518997192},{"id":"https://openalex.org/keywords/programmable-logic-controller","display_name":"Programmable logic controller","score":0.7231687903404236},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.682476818561554},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6782127022743225},{"id":"https://openalex.org/keywords/simple-programmable-logic-device","display_name":"Simple programmable logic device","score":0.6627779006958008},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6614646911621094},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.6285063028335571},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.5824335217475891},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.5729932188987732},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.534027099609375},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.5290120244026184},{"id":"https://openalex.org/keywords/erasable-programmable-logic-device","display_name":"Erasable programmable logic device","score":0.4941416084766388},{"id":"https://openalex.org/keywords/control-logic","display_name":"Control logic","score":0.46212172508239746},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4508762061595917},{"id":"https://openalex.org/keywords/macrocell-array","display_name":"Macrocell array","score":0.4450996220111847},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4149032533168793},{"id":"https://openalex.org/keywords/control-system","display_name":"Control system","score":0.41365569829940796},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41284382343292236},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2740693688392639},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.23624476790428162},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1926056146621704},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.11754095554351807},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10294201970100403},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.09810590744018555},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.0633857250213623}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8833142518997192},{"id":"https://openalex.org/C37374048","wikidata":"https://www.wikidata.org/wiki/Q188674","display_name":"Programmable logic controller","level":2,"score":0.7231687903404236},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.682476818561554},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6782127022743225},{"id":"https://openalex.org/C34370810","wikidata":"https://www.wikidata.org/wiki/Q3961319","display_name":"Simple programmable logic device","level":5,"score":0.6627779006958008},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6614646911621094},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.6285063028335571},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.5824335217475891},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.5729932188987732},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.534027099609375},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.5290120244026184},{"id":"https://openalex.org/C110050671","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Erasable programmable logic device","level":5,"score":0.4941416084766388},{"id":"https://openalex.org/C2776350369","wikidata":"https://www.wikidata.org/wiki/Q843479","display_name":"Control logic","level":2,"score":0.46212172508239746},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4508762061595917},{"id":"https://openalex.org/C142278197","wikidata":"https://www.wikidata.org/wiki/Q4284934","display_name":"Macrocell array","level":5,"score":0.4450996220111847},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4149032533168793},{"id":"https://openalex.org/C17500928","wikidata":"https://www.wikidata.org/wiki/Q959968","display_name":"Control system","level":2,"score":0.41365569829940796},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41284382343292236},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2740693688392639},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.23624476790428162},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1926056146621704},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.11754095554351807},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10294201970100403},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.09810590744018555},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0633857250213623},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tie.2014.2362888","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tie.2014.2362888","pdf_url":null,"source":{"id":"https://openalex.org/S58031724","display_name":"IEEE Transactions on Industrial Electronics","issn_l":"0278-0046","issn":["0278-0046","1557-9948"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Industrial Electronics","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4099999964237213,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W152827354","https://openalex.org/W1544832437","https://openalex.org/W1578111053","https://openalex.org/W1887744064","https://openalex.org/W1976019805","https://openalex.org/W1985340760","https://openalex.org/W1985673483","https://openalex.org/W1986836693","https://openalex.org/W2003618327","https://openalex.org/W2014798747","https://openalex.org/W2030402004","https://openalex.org/W2038318015","https://openalex.org/W2082100948","https://openalex.org/W2082744949","https://openalex.org/W2093099566","https://openalex.org/W2098922153","https://openalex.org/W2100183523","https://openalex.org/W2100821909","https://openalex.org/W2106200299","https://openalex.org/W2126656927","https://openalex.org/W2129788823","https://openalex.org/W2150641515","https://openalex.org/W2157505081","https://openalex.org/W2159910998","https://openalex.org/W2160588944","https://openalex.org/W2162585354","https://openalex.org/W2337156847","https://openalex.org/W6634407512","https://openalex.org/W6646664106","https://openalex.org/W6651253826"],"related_works":["https://openalex.org/W1904803855","https://openalex.org/W1528933814","https://openalex.org/W2028109223","https://openalex.org/W3117015220","https://openalex.org/W2038293309","https://openalex.org/W1541210136","https://openalex.org/W3163714531","https://openalex.org/W2145701142","https://openalex.org/W2096402241","https://openalex.org/W2021058029"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,20,33,62,75],"design":[4],"and":[5,44,47,66],"implementation":[6],"of":[7,19,35,38,74],"a":[8,52],"multiprocessor":[9],"programmable":[10,90],"controller":[11,57],"in":[12,32,51,70],"field-programmable":[13],"gate":[14],"array":[15],"(FPGA).":[16],"The":[17,56],"novelty":[18],"proposed":[21],"solution":[22],"is":[23,58,80],"that":[24,78],"it":[25,79],"combines":[26],"two":[27],"approaches":[28],"used":[29],"so":[30],"far":[31],"domain":[34],"FPGA":[36,54],"implementations":[37],"control":[39,68,84],"algorithms,":[40],"i.e.,":[41],"program":[42],"based":[43],"hardware":[45],"coded,":[46],"applies":[48],"multiple":[49],"processors":[50],"single":[53],"chip.":[55],"programmed":[59],"according":[60],"to":[61,82],"IEC":[63],"61131-3":[64],"standard":[65],"runs":[67],"tasks":[69],"parallel.":[71],"Performance":[72],"tests":[73],"prototype":[76],"show":[77],"able":[81],"execute":[83],"programs":[85],"significantly":[86],"faster":[87],"than":[88],"industrial":[89],"logic":[91],"controllers.":[92]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":8},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":6},{"year":2017,"cited_by_count":9},{"year":2016,"cited_by_count":7},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}