{"id":"https://openalex.org/W4319777763","doi":"https://doi.org/10.1109/tetc.2023.3242555","title":"Path-Based Delay Variation Models for Parallel-Prefix Adders","display_name":"Path-Based Delay Variation Models for Parallel-Prefix Adders","publication_year":2023,"publication_date":"2023-02-09","ids":{"openalex":"https://openalex.org/W4319777763","doi":"https://doi.org/10.1109/tetc.2023.3242555"},"language":"en","primary_location":{"id":"doi:10.1109/tetc.2023.3242555","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tetc.2023.3242555","pdf_url":null,"source":{"id":"https://openalex.org/S2496326734","display_name":"IEEE Transactions on Emerging Topics in Computing","issn_l":"2168-6750","issn":["2168-6750","2376-4562"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Emerging Topics in Computing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062509095","display_name":"Kleanthis Papachatzopoulos","orcid":"https://orcid.org/0000-0002-1193-7611"},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Kleanthis Papachatzopoulos","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Patras, Patras, Greece"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Patras, Patras, Greece","institution_ids":["https://openalex.org/I174878644"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021252086","display_name":"Vassilis Paliouras","orcid":"https://orcid.org/0000-0002-1414-7500"},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Vassilis Paliouras","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Patras, Patras, Greece"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Patras, Patras, Greece","institution_ids":["https://openalex.org/I174878644"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5062509095"],"corresponding_institution_ids":["https://openalex.org/I174878644"],"apc_list":null,"apc_paid":null,"fwci":0.4016,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.57649172,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"11","issue":"3","first_page":"689","last_page":"705"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.742063045501709},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6241673827171326},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5700342655181885},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.5699262619018555},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5050814747810364},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.5016703605651855},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.4718095064163208},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.313213586807251},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2289910614490509},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.1557871699333191},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.14312008023262024}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.742063045501709},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6241673827171326},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5700342655181885},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.5699262619018555},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5050814747810364},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.5016703605651855},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.4718095064163208},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.313213586807251},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2289910614490509},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.1557871699333191},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.14312008023262024},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tetc.2023.3242555","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tetc.2023.3242555","pdf_url":null,"source":{"id":"https://openalex.org/S2496326734","display_name":"IEEE Transactions on Emerging Topics in Computing","issn_l":"2168-6750","issn":["2168-6750","2376-4562"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Emerging Topics in Computing","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":39,"referenced_works":["https://openalex.org/W612784192","https://openalex.org/W1530625153","https://openalex.org/W1582324226","https://openalex.org/W1924196901","https://openalex.org/W1963965124","https://openalex.org/W1997582549","https://openalex.org/W1997782294","https://openalex.org/W2007353624","https://openalex.org/W2026746601","https://openalex.org/W2035894108","https://openalex.org/W2059193309","https://openalex.org/W2060002782","https://openalex.org/W2074224805","https://openalex.org/W2095665333","https://openalex.org/W2097193789","https://openalex.org/W2097414281","https://openalex.org/W2131647018","https://openalex.org/W2134141201","https://openalex.org/W2135880741","https://openalex.org/W2139482847","https://openalex.org/W2143462372","https://openalex.org/W2147847555","https://openalex.org/W2152473162","https://openalex.org/W2153878017","https://openalex.org/W2155469874","https://openalex.org/W2168543008","https://openalex.org/W2342528869","https://openalex.org/W2460271409","https://openalex.org/W2572235427","https://openalex.org/W2604956773","https://openalex.org/W2795745426","https://openalex.org/W2803057706","https://openalex.org/W2922420481","https://openalex.org/W2943441500","https://openalex.org/W3016582401","https://openalex.org/W3047200798","https://openalex.org/W3140201352","https://openalex.org/W3212488318","https://openalex.org/W4312520638"],"related_works":["https://openalex.org/W2107551409","https://openalex.org/W1973774436","https://openalex.org/W3092420867","https://openalex.org/W2115729972","https://openalex.org/W2042032654","https://openalex.org/W2123535323","https://openalex.org/W2158291854","https://openalex.org/W2165340891","https://openalex.org/W2134944363","https://openalex.org/W1804063983"],"abstract_inverted_index":{"State-of-the-art":[0],"static":[1],"timing":[2,173],"analysis":[3],"algorithms":[4],"can":[5],"evaluate":[6],"worst-case":[7],"delay":[8,46,80,123,221],"in":[9],"statistical":[10],"terms.":[11],"In":[12],"this":[13],"paper,":[14],"a":[15,57,104,116,154,177,219],"modeling":[16],"framework":[17],"is":[18,50,129,205],"introduced":[19,91,114,148,168],"for":[20,84,131,153,187,201,211,218],"the":[21,24,44,54,63,71,85,98,110,113,120,159,167,171,188,196,209,212],"evaluation":[22],"of":[23,30,33,47,56,59,88,103,112,119,195,214,226],"maximum-delay":[25,65,99],"Cumulative":[26],"Density":[27],"Function":[28],"(CDF)":[29],"an":[31,193],"ensemble":[32],"parallel-prefix":[34,48,133],"adder":[35],"topologies.":[36],"For":[37,158],"moderate":[38],"variations":[39,136],"and":[40,74,142,163,223],"close-to-nominal":[41],"supply":[42],"voltages,":[43],"maximum":[45,55,215],"adders":[49],"practically":[51],"determined":[52],"by":[53,101],"set":[58,87],"near-critical-delay":[60],"paths":[61,68],"around":[62],"nominal":[64,160],"path.":[66],"These":[67],"end":[69,203],"to":[70,96,149,184,199],"most":[72],"significant":[73],"neighboring":[75],"bit":[76],"positions.":[77],"Matrix-based":[78],"path":[79],"formulations":[81,93],"are":[82,94,143],"derived":[83],"particular":[86],"paths.":[89],"The":[90],"matrix":[92],"exploited":[95],"assess":[97],"CDF":[100],"means":[102],"multivariate":[105],"Gaussian":[106,146],"CDF.":[107],"To":[108],"validate":[109],"accuracy":[111],"models,":[115],"quantitative":[117],"comparison":[118],"proposed":[121,197],"probabilistic":[122],"models":[124,152,169],"against":[125],"Spice-level":[126,185],"Monte-Carlo":[127],"simulations":[128,186],"offered":[130],"certain":[132,224],"adders.":[134],"Threshold-voltage":[135],"summarize":[137],"several":[138],"process-dependent":[139],"variation-inducing":[140],"mechanisms":[141],"modeled":[144],"as":[145],"variations,":[147,166],"BSIM-4":[150],"transistor":[151],"16-nm":[155],"technology":[156],"node.":[157],"voltage":[161],"case":[162],"10%":[164],"threshold-voltage":[165],"estimate":[170],"0.95":[172],"yield":[174],"point":[175],"with":[176],"mean":[178],"absolute":[179],"error":[180,210],"below":[181],"1%":[182],"compared":[183],"16":[189],"bit-length":[190],"case.":[191],"Furthermore,":[192],"extension":[194],"approach":[198],"account":[200],"multiple":[202],"points":[204],"investigated":[206],"that":[207],"reduces":[208],"estimation":[213],"delay,":[216],"demonstrated":[217],"unit":[220],"model":[222],"bit-lengths":[225],"Kogge-Stone":[227],"adder.":[228]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
