{"id":"https://openalex.org/W3016582401","doi":"https://doi.org/10.1109/tetc.2020.2987946","title":"A Statistical Gate Sizing Method for Timing Yield and Lifetime Reliability Optimization of Integrated Circuits","display_name":"A Statistical Gate Sizing Method for Timing Yield and Lifetime Reliability Optimization of Integrated Circuits","publication_year":2020,"publication_date":"2020-04-16","ids":{"openalex":"https://openalex.org/W3016582401","doi":"https://doi.org/10.1109/tetc.2020.2987946","mag":"3016582401"},"language":"en","primary_location":{"id":"doi:10.1109/tetc.2020.2987946","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tetc.2020.2987946","pdf_url":null,"source":{"id":"https://openalex.org/S2496326734","display_name":"IEEE Transactions on Emerging Topics in Computing","issn_l":"2168-6750","issn":["2168-6750","2376-4562"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Emerging Topics in Computing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014885841","display_name":"Seyed Milad Ebrahimipour","orcid":null},"institutions":[{"id":"https://openalex.org/I115566878","display_name":"Shahid Bahonar University of Kerman","ror":"https://ror.org/04zn42r77","country_code":"IR","type":"education","lineage":["https://openalex.org/I115566878"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"S. M. Ebrahimipour","raw_affiliation_strings":["Department of Computer Engineering, Faculty of Engineering, Shahid Bahonar University of Kerman, Kerman, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Faculty of Engineering, Shahid Bahonar University of Kerman, Kerman, Iran","institution_ids":["https://openalex.org/I115566878"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028010546","display_name":"Behnam Ghavami","orcid":"https://orcid.org/0000-0001-5391-383X"},"institutions":[{"id":"https://openalex.org/I115566878","display_name":"Shahid Bahonar University of Kerman","ror":"https://ror.org/04zn42r77","country_code":"IR","type":"education","lineage":["https://openalex.org/I115566878"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Behnam Ghavami","raw_affiliation_strings":["Department of Computer Engineering, Faculty of Engineering, Shahid Bahonar University of Kerman, Kerman, Iran"],"raw_orcid":"https://orcid.org/0000-0001-5391-383X","affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Faculty of Engineering, Shahid Bahonar University of Kerman, Kerman, Iran","institution_ids":["https://openalex.org/I115566878"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5078040742","display_name":"Mohsen Raji","orcid":"https://orcid.org/0000-0001-7113-5197"},"institutions":[{"id":"https://openalex.org/I166459259","display_name":"Shiraz University","ror":"https://ror.org/028qtbk54","country_code":"IR","type":"education","lineage":["https://openalex.org/I166459259"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Mohsen Raji","raw_affiliation_strings":["School of Electrical and Computer Engineering, Shiraz University, Shiraz, Iran"],"raw_orcid":"https://orcid.org/0000-0001-7113-5197","affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Shiraz University, Shiraz, Iran","institution_ids":["https://openalex.org/I166459259"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.8075,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.71438622,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":98},"biblio":{"volume":"9","issue":"2","first_page":"759","last_page":"773"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6711595058441162},{"id":"https://openalex.org/keywords/circuit-reliability","display_name":"Circuit reliability","score":0.5059360861778259},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.5018184185028076},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.498873233795166},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.4846120774745941},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.4578292965888977},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.449729859828949},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.43619608879089355},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4320931136608124},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.38540923595428467},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15772053599357605},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13603359460830688},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1351989507675171}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6711595058441162},{"id":"https://openalex.org/C2778309119","wikidata":"https://www.wikidata.org/wiki/Q5121614","display_name":"Circuit reliability","level":4,"score":0.5059360861778259},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.5018184185028076},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.498873233795166},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.4846120774745941},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.4578292965888977},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.449729859828949},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.43619608879089355},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4320931136608124},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.38540923595428467},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15772053599357605},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13603359460830688},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1351989507675171},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tetc.2020.2987946","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tetc.2020.2987946","pdf_url":null,"source":{"id":"https://openalex.org/S2496326734","display_name":"IEEE Transactions on Emerging Topics in Computing","issn_l":"2168-6750","issn":["2168-6750","2376-4562"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Emerging Topics in Computing","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":43,"referenced_works":["https://openalex.org/W1782430720","https://openalex.org/W1901339374","https://openalex.org/W1966741973","https://openalex.org/W1967709031","https://openalex.org/W1972242240","https://openalex.org/W2009592036","https://openalex.org/W2013135496","https://openalex.org/W2042566540","https://openalex.org/W2047663435","https://openalex.org/W2069345435","https://openalex.org/W2081215702","https://openalex.org/W2081382200","https://openalex.org/W2093149861","https://openalex.org/W2095804030","https://openalex.org/W2100661413","https://openalex.org/W2102729267","https://openalex.org/W2103792078","https://openalex.org/W2113728962","https://openalex.org/W2117648153","https://openalex.org/W2119225580","https://openalex.org/W2119958333","https://openalex.org/W2120116751","https://openalex.org/W2120490615","https://openalex.org/W2134067926","https://openalex.org/W2134777311","https://openalex.org/W2163262735","https://openalex.org/W2163430596","https://openalex.org/W2165130438","https://openalex.org/W2284954312","https://openalex.org/W2293356837","https://openalex.org/W2309928151","https://openalex.org/W2344758701","https://openalex.org/W2396345169","https://openalex.org/W2407955805","https://openalex.org/W2412767444","https://openalex.org/W2768326850","https://openalex.org/W2782496992","https://openalex.org/W2802272371","https://openalex.org/W2899297761","https://openalex.org/W4205623694","https://openalex.org/W4249551816","https://openalex.org/W4254506919","https://openalex.org/W6675497357"],"related_works":["https://openalex.org/W2378211422","https://openalex.org/W2745001401","https://openalex.org/W4321353415","https://openalex.org/W2130974462","https://openalex.org/W1975778413","https://openalex.org/W1975511343","https://openalex.org/W4312239443","https://openalex.org/W2093227051","https://openalex.org/W3152064381","https://openalex.org/W2037773470"],"abstract_inverted_index":{"As":[0],"CMOS":[1],"devices":[2],"become":[3,9],"smaller,":[4],"process":[5,43,82],"and":[6,16,45,81,93,119,135],"aging":[7,80,91],"variations":[8],"a":[10,23],"major":[11],"issue":[12],"for":[13],"circuit":[14,37,57],"reliability":[15,34,144],"yield.":[17],"In":[18,48,156],"this":[19,85],"paper,":[20],"we":[21,73],"propose":[22],"new":[24],"two-phase":[25],"gate":[26,96,105],"sizing":[27,106],"approach":[28,164],"in":[29,69],"order":[30],"to":[31,60,103],"improve":[32,61],"the":[33,36,39,49,52,56,62,66,70,75,125,129,136,142,147,159,162],"of":[35,42,55,65,149],"considering":[38],"joint":[40],"effect":[41],"variation":[44],"transistor":[46],"aging.":[47],"first":[50],"stage,":[51,72],"initial":[53],"delay":[54,76,94],"is":[58],"optimized":[59],"timing":[63,132,139],"yield":[64,133],"circuit.":[67],"Then,":[68],"second":[71],"reduce":[74],"degradation":[77],"induced":[78],"by":[79],"variations.":[83],"To":[84],"end,":[86],"two":[87],"novel":[88],"concepts":[89],"called":[90],"probability":[92],"degradation-aware":[95],"criticality":[97],"are":[98],"introduced":[99],"which":[100],"enable":[101],"us":[102],"perform":[104],"efficiently":[107],"using":[108],"an":[109],"adaptive":[110],"multi-objective":[111],"ranking":[112],"approach.":[113],"Experimental":[114],"results":[115],"based":[116],"on":[117,154],"ISCAS'85":[118],"EPFL":[120],"benchmark":[121],"circuits":[122],"show":[123],"that,":[124],"proposed":[126,163],"method":[127],"achieves":[128],"95":[130],"percent":[131,138,151],"constraint":[134,145],"10":[137],"guard-band":[140],"as":[141],"lifetime":[143],"at":[146],"expense":[148],"13.72":[150],"area":[152,167],"overhead,":[153],"average.":[155],"comparison":[157],"with":[158,169],"state-of-the-art":[160],"methods,":[161],"imposes":[165],"lower":[166],"overhead":[168],"acceptable":[170],"runtime.":[171]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":2}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}