{"id":"https://openalex.org/W2564058967","doi":"https://doi.org/10.1109/tetc.2016.2644381","title":"SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC","display_name":"SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC","publication_year":2016,"publication_date":"2016-12-23","ids":{"openalex":"https://openalex.org/W2564058967","doi":"https://doi.org/10.1109/tetc.2016.2644381","mag":"2564058967"},"language":"en","primary_location":{"id":"doi:10.1109/tetc.2016.2644381","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tetc.2016.2644381","pdf_url":null,"source":{"id":"https://openalex.org/S2496326734","display_name":"IEEE Transactions on Emerging Topics in Computing","issn_l":"2168-6750","issn":["2168-6750","2376-4562"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Emerging Topics in Computing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069159349","display_name":"Vin\u00edcius Dal","orcid":null},"institutions":[{"id":"https://openalex.org/I47403697","display_name":"Instituto Federal de Educa\u00e7\u00e3o, Ci\u00eancia e Tecnologia de Santa Catarina","ror":"https://ror.org/00fcpmw49","country_code":"BR","type":"education","lineage":["https://openalex.org/I47403697"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Vinicius Dal Bem","raw_affiliation_strings":["Federal Institute of Santa Catarina, Xanxer\u00ea/SC, Brazil"],"affiliations":[{"raw_affiliation_string":"Federal Institute of Santa Catarina, Xanxer\u00ea/SC, Brazil","institution_ids":["https://openalex.org/I47403697"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010444815","display_name":"Felipe S. Marranghello","orcid":"https://orcid.org/0000-0002-5368-6750"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Felipe S. Marranghello","raw_affiliation_strings":["PGMicro, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre/RS, Brazil"],"affiliations":[{"raw_affiliation_string":"PGMicro, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre/RS, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065397615","display_name":"Andr\u00e9 I. Reis","orcid":"https://orcid.org/0000-0002-3118-8160"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Andre I. Reis","raw_affiliation_strings":["PGMicro, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre/RS, Brazil"],"affiliations":[{"raw_affiliation_string":"PGMicro, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre/RS, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090563366","display_name":"Renato P. Ribas","orcid":"https://orcid.org/0000-0002-9895-7489"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Renato P. Ribas","raw_affiliation_strings":["PGMicro, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre/RS, Brazil"],"affiliations":[{"raw_affiliation_string":"PGMicro, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre/RS, Brazil","institution_ids":["https://openalex.org/I130442723"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5069159349"],"corresponding_institution_ids":["https://openalex.org/I47403697"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.14383231,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"5","issue":"2","first_page":"247","last_page":"259"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7501600980758667},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.7364335656166077},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.6083909273147583},{"id":"https://openalex.org/keywords/boolean-satisfiability-problem","display_name":"Boolean satisfiability problem","score":0.5813857316970825},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5789610743522644},{"id":"https://openalex.org/keywords/solver","display_name":"Solver","score":0.5566681027412415},{"id":"https://openalex.org/keywords/quadratic-growth","display_name":"Quadratic growth","score":0.5008289813995361},{"id":"https://openalex.org/keywords/satisfiability-modulo-theories","display_name":"Satisfiability modulo theories","score":0.42283904552459717},{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.41322508454322815},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38629966974258423},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.33313870429992676},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.33082032203674316},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32909584045410156},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.20269230008125305},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18556883931159973},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.10219749808311462}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7501600980758667},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.7364335656166077},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.6083909273147583},{"id":"https://openalex.org/C6943359","wikidata":"https://www.wikidata.org/wiki/Q875276","display_name":"Boolean satisfiability problem","level":2,"score":0.5813857316970825},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5789610743522644},{"id":"https://openalex.org/C2778770139","wikidata":"https://www.wikidata.org/wiki/Q1966904","display_name":"Solver","level":2,"score":0.5566681027412415},{"id":"https://openalex.org/C195956108","wikidata":"https://www.wikidata.org/wiki/Q7268362","display_name":"Quadratic growth","level":2,"score":0.5008289813995361},{"id":"https://openalex.org/C164155591","wikidata":"https://www.wikidata.org/wiki/Q2067766","display_name":"Satisfiability modulo theories","level":2,"score":0.42283904552459717},{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.41322508454322815},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38629966974258423},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.33313870429992676},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.33082032203674316},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32909584045410156},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.20269230008125305},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18556883931159973},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.10219749808311462},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tetc.2016.2644381","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tetc.2016.2644381","pdf_url":null,"source":{"id":"https://openalex.org/S2496326734","display_name":"IEEE Transactions on Emerging Topics in Computing","issn_l":"2168-6750","issn":["2168-6750","2376-4562"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Emerging Topics in Computing","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321091","display_name":"Coordena\u00e7\u00e3o de Aperfei\u00e7oamento de Pessoal de N\u00edvel Superior","ror":"https://ror.org/00x0ma614"},{"id":"https://openalex.org/F4320322025","display_name":"Conselho Nacional de Desenvolvimento Cient\u00edfico e Tecnol\u00f3gico","ror":"https://ror.org/03swz6y49"},{"id":"https://openalex.org/F4320334960","display_name":"Seventh Framework Programme","ror":"https://ror.org/00k4n6c32"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W161930826","https://openalex.org/W1519908293","https://openalex.org/W1962191900","https://openalex.org/W1965232212","https://openalex.org/W1971495518","https://openalex.org/W1978155484","https://openalex.org/W2001255866","https://openalex.org/W2009196135","https://openalex.org/W2018989845","https://openalex.org/W2026369926","https://openalex.org/W2035113414","https://openalex.org/W2035183087","https://openalex.org/W2040537281","https://openalex.org/W2041626447","https://openalex.org/W2050867169","https://openalex.org/W2090128096","https://openalex.org/W2107511488","https://openalex.org/W2109887272","https://openalex.org/W2115092649","https://openalex.org/W2116625560","https://openalex.org/W2124007645","https://openalex.org/W2137061498","https://openalex.org/W2138876803","https://openalex.org/W2153778369","https://openalex.org/W3144063603","https://openalex.org/W3150660474","https://openalex.org/W4241865974","https://openalex.org/W4242098806","https://openalex.org/W4255539687","https://openalex.org/W6837167634"],"related_works":["https://openalex.org/W2788804672","https://openalex.org/W1945774704","https://openalex.org/W1505872263","https://openalex.org/W4241145878","https://openalex.org/W2141151670","https://openalex.org/W2956134060","https://openalex.org/W4285064683","https://openalex.org/W2963523951","https://openalex.org/W1572868659","https://openalex.org/W2942592915"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,97],"SAT-based":[4],"formulation":[5,29,70],"to":[6,20,33,76],"evaluate":[7],"the":[8,34,40,61,68,77,82,89,93,101],"logical":[9],"capacity":[10],"of":[11,63,79,92],"VIA-configurable":[12],"block":[13],"templates.":[14],"The":[15,26],"proposed":[16,27],"solution":[17],"is":[18],"able":[19],"support":[21],"any":[22],"user-defined":[23],"regular":[24],"layout.":[25],"SAT":[28,69,94],"was":[30],"sucessufully":[31],"applied":[32],"three":[35],"main":[36],"VCSA":[37,83,103],"fabrics":[38],"in":[39,67,81],"literature":[41],"considering":[42],"transistor":[43,51],"networks":[44,52],"from":[45],"an":[46],"open":[47],"cell":[48],"library":[49],"and":[50,65],"representing":[53],"all":[54],"4-input":[55],"Boolean":[56],"functions.":[57],"We":[58,85],"observed":[59],"that":[60,88],"number":[62,78],"literals":[64],"variables":[66],"grows":[71],"nearly":[72],"quadratically":[73],"with":[74],"respect":[75],"transistors":[80],"fabric.":[84,104],"also":[86],"noticed":[87],"average":[90],"runtime":[91],"solver":[95],"presents":[96],"strong":[98],"dependence":[99],"on":[100],"input":[102]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}