{"id":"https://openalex.org/W2557101570","doi":"https://doi.org/10.1109/tetc.2016.2630121","title":"A High-Performance FPGA Architecture Using One-Level RRAM-Based Multiplexers","display_name":"A High-Performance FPGA Architecture Using One-Level RRAM-Based Multiplexers","publication_year":2016,"publication_date":"2016-11-17","ids":{"openalex":"https://openalex.org/W2557101570","doi":"https://doi.org/10.1109/tetc.2016.2630121","mag":"2557101570"},"language":"en","primary_location":{"id":"doi:10.1109/tetc.2016.2630121","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tetc.2016.2630121","pdf_url":null,"source":{"id":"https://openalex.org/S2496326734","display_name":"IEEE Transactions on Emerging Topics in Computing","issn_l":"2168-6750","issn":["2168-6750","2376-4562"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Emerging Topics in Computing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://infoscience.epfl.ch/record/224321","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103004961","display_name":"Xifan Tang","orcid":"https://orcid.org/0000-0003-2203-3981"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"Xifan Tang","raw_affiliation_strings":["Integrated Systems Laboratory, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Vaud, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Vaud, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072927296","display_name":"Giovanni De Micheli","orcid":"https://orcid.org/0000-0002-7827-3215"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Giovanni De Micheli","raw_affiliation_strings":["Integrated Systems Laboratory, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Vaud, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Vaud, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002568331","display_name":"Pierre\u2010Emmanuel Gaillardon","orcid":"https://orcid.org/0000-0003-3634-3999"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pierre-Emmanuel Gaillardon","raw_affiliation_strings":["Laboratory for NanoIntegrated Systems, University of Utah, Salt Lake City, UT"],"affiliations":[{"raw_affiliation_string":"Laboratory for NanoIntegrated Systems, University of Utah, Salt Lake City, UT","institution_ids":["https://openalex.org/I223532165"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5103004961"],"corresponding_institution_ids":["https://openalex.org/I5124864"],"apc_list":null,"apc_paid":null,"fwci":0.9188,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.78666502,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"5","issue":"2","first_page":"210","last_page":"222"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.9444754123687744},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.7542189359664917},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7309910655021667},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6777279376983643},{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.610531210899353},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5848885774612427},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5445123910903931},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.533342182636261},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.47737690806388855},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.4713059365749359},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38791993260383606},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3707416355609894},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.36090248823165894},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.2958090901374817},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.25235238671302795},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21304330229759216},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.164331316947937},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11091235280036926}],"concepts":[{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.9444754123687744},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.7542189359664917},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7309910655021667},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6777279376983643},{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.610531210899353},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5848885774612427},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5445123910903931},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.533342182636261},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.47737690806388855},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.4713059365749359},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38791993260383606},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3707416355609894},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36090248823165894},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.2958090901374817},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.25235238671302795},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21304330229759216},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.164331316947937},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11091235280036926},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tetc.2016.2630121","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tetc.2016.2630121","pdf_url":null,"source":{"id":"https://openalex.org/S2496326734","display_name":"IEEE Transactions on Emerging Topics in Computing","issn_l":"2168-6750","issn":["2168-6750","2376-4562"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Emerging Topics in Computing","raw_type":"journal-article"},{"id":"pmh:oai:infoscience.epfl.ch:224321","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/224321","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},{"id":"pmh:oai:infoscience.tind.io:224321","is_oa":true,"landing_page_url":"https://infoscience.epfl.ch/handle/20.500.14299/132759","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"research article"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:224321","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/224321","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.4000000059604645}],"awards":[{"id":"https://openalex.org/G6748573657","display_name":null,"funder_award_id":"200021-146600","funder_id":"https://openalex.org/F4320320924","funder_display_name":"Schweizerischer Nationalfonds zur F\u00f6rderung der Wissenschaftlichen Forschung"}],"funders":[{"id":"https://openalex.org/F4320320924","display_name":"Schweizerischer Nationalfonds zur F\u00f6rderung der Wissenschaftlichen Forschung","ror":"https://ror.org/00yjd3n13"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":35,"referenced_works":["https://openalex.org/W1480183640","https://openalex.org/W1523051745","https://openalex.org/W1641127476","https://openalex.org/W1971000062","https://openalex.org/W1981321271","https://openalex.org/W1984588379","https://openalex.org/W1987760418","https://openalex.org/W2004823737","https://openalex.org/W2019965721","https://openalex.org/W2020003503","https://openalex.org/W2023146792","https://openalex.org/W2030765577","https://openalex.org/W2040166817","https://openalex.org/W2055411146","https://openalex.org/W2078177817","https://openalex.org/W2086709250","https://openalex.org/W2089090392","https://openalex.org/W2105281355","https://openalex.org/W2120452158","https://openalex.org/W2120544688","https://openalex.org/W2138383740","https://openalex.org/W2138840350","https://openalex.org/W2139580250","https://openalex.org/W2146437820","https://openalex.org/W2168972302","https://openalex.org/W2194966023","https://openalex.org/W2263042501","https://openalex.org/W2292257019","https://openalex.org/W2342821294","https://openalex.org/W3140396777","https://openalex.org/W4214686615","https://openalex.org/W4243164749","https://openalex.org/W6628664065","https://openalex.org/W6681989696","https://openalex.org/W7054665252"],"related_works":["https://openalex.org/W3005999147","https://openalex.org/W3176428941","https://openalex.org/W3089883684","https://openalex.org/W2004526657","https://openalex.org/W4232634182","https://openalex.org/W4301187613","https://openalex.org/W2923038022","https://openalex.org/W3008646524","https://openalex.org/W4385624997","https://openalex.org/W2593506445"],"abstract_inverted_index":{"Resistive":[0],"Random":[1],"Access":[2],"Memory":[3],"(RRAM)-based":[4],"routing":[5,98],"multiplexers,":[6,88],"built":[7],"using":[8],"a":[9,77,109,140,169,220,224],"one-level":[10,110],"structure,":[11],"are":[12],"significantly":[13],"more":[14],"delay":[15,31,62,74,160,184],"efficient":[16],"than":[17,42,55],"state-of-art":[18,78],"SRAM-based":[19,43,57,221],"implementations":[20],"thanks":[21],"to":[22,39,51,82,103,219],"their":[23,56],"lower":[24],"achievable":[25],"on-state":[26],"resistance.":[27],"In":[28,64],"addition,":[29],"the":[30,71,73,84,200],"of":[32,76,86,113,136],"RRAM-based":[33,48,79,87,151,202],"multiplexers":[34,54],"scales":[35],"better":[36],"with":[37,164],"respect":[38],"input":[40],"size":[41],"multiplexers.":[44],"This":[45],"property":[46],"allows":[47],"FPGA":[49,93,203,222],"architectures":[50],"employ":[52,126],"larger":[53,127],"counterparts,":[58],"without":[59],"generating":[60],"any":[61],"overhead.":[63],"this":[65],"paper,":[66],"we":[67,89],"first":[68],"evaluate":[69],"at":[70],"circuit-level":[72],"improvements":[75],"multiplexer.":[80],"Then,":[81],"unlock":[83],"potential":[85],"propose":[90],"three":[91],"related":[92],"architecture":[94,142,204],"optimizations:":[95],"(a)":[96],"The":[97,121,173],"tracks":[99],"should":[100,125,132],"be":[101,133],"interconnected":[102],"Look-Up":[104],"Table":[105],"(LUT)":[106],"inputs":[107],"via":[108],"crossbar,":[111],"instead":[112,135],"through":[114],"Connection":[115],"Blocks":[116],"and":[117,148,159,188,197,211],"local":[118],"routing;":[119],"(b)":[120],"Switch":[122],"Block":[123],"(SB)":[124],"multiplexers;":[128],"(c)":[129],"Length-2":[130],"wires":[131],"used":[134],"length-4":[137],"wires.":[138],"When":[139],"classical":[141,225],"is":[143],"considered":[144],"for":[145,168],"both":[146],"SRAM":[147],"RRAM":[149,195],"technologies,":[150],"FPGAs":[152],"can":[153,177],"reduce":[154],"area":[155,180],"by":[156,161,181,185,191,208,214],"17":[157],"percent":[158,163,187,210],"32":[162],"zero":[165],"power":[166],"overhead":[167],"40":[170],"nm":[171],"technology.":[172],"proposed":[174,201],"architectural":[175,198],"enhancements":[176],"further":[178],"improve":[179],"15":[182],"percent,":[183,216],"10":[186],"channel":[189],"width":[190],"13":[192],"percent.":[193],"Combining":[194],"technology":[196],"enhancements,":[199],"improves":[205],"Area-Delay":[206],"Product":[207,213],"57":[209],"Delay-Power":[212],"38":[215],"as":[217],"compared":[218],"exploiting":[223],"architecture.":[226]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
